High electron mobility transistor circuit

1. A transistor circuit comprising:

a first high electron mobility transistor; and

a second high electron mobility transistor having a negative threshold voltage,

wherein a source of the second high electron mobility transistor is coupled to a gate of the first high electron mobility transistor, and

a gate of the second high electron mobility transistor is coupled to a source of the first high electron mobility transistor.

2. The transistor circuit according to claim 1 ,

wherein the first high electron mobility transistor includes a first field plate including at least a portion extending between the gate and the drain thereof.

3. The transistor circuit according to claim 2 ,

wherein the first high electron mobility transistor further includes a second field plate including at least a portion extending between the first field plate and the drain thereof.

4. The transistor circuit according to claim 1 ,

wherein the second high electron mobility transistor includes a field plate including at least a portion extending between the gate and the drain thereof and being coupled to the source of the first high electron mobility transistor.

5. The transistor circuit according to claims 1 , further comprising:

a third high electron mobility transistor coupled in series to the second high electron mobility transistor,

wherein the third high electron mobility transistor includes a gate coupled to the drain of the first high electron mobility transistor, and has a negative threshold voltage.

6. The transistor circuit according to claim 1 ,

wherein the second high electron mobility transistor limits a voltage between the source and the gate of the first high electron mobility transistor to a voltage smaller than a gate withstand voltage of the first high electron mobility transistor.