Method for fabricating semiconductor device with buried word line

1. A method for fabricating a semiconductor device, comprising:

etching a substrate to form a plurality of bodies isolated by a first trench;

forming a buried bit line gap-filling a portion of the first trench;

etching the top portions of the bodies to form a plurality of pillars isolated by a plurality of second trenches extending across the first trench;

forming a passivation layer gap-filling a portion of the second trenches;

forming an isolation layer that divides each of the second trenches into isolation trenches over the passivation layer; and

filling a portion of the isolation trenches to form a buried word line extending in a direction crossing over the buried bit line after the forming the isolation layer.

2. The method of claim 1 , wherein the forming of the pillars comprises:

forming a dielectric layer gap-filling the first trench over the entire surface including the buried bit line; and

forming the second trenches by etching one of the bodies and the dielectric layer to expose the surface of the buried bit line.

3. The method of claim 1 , wherein the forming of the passivation layer comprises:

forming a dielectric layer to gap-fill the second trenches; and

etching back the dielectric layer.

4. The method of claim 3 , wherein the passivation layer comprises an oxide layer.

5. The method of claim 1 , wherein the forming of the isolation layer comprises:

forming spacers along both sidewalls of the second trenches over the passivation layer;

forming a dielectric layer gap-filling the second trenches having the spacers formed therein; and

selectively removing the spacers to form the isolation trenches.

6. The method of claim 5 , wherein the isolation layer comprises an oxide layer.

7. The method of claim 5 , wherein the removing of the spacers is performed through a wet etching process.

8. The method of claim 1 , wherein the forming of the buried word line comprises:

forming a conductive layer to gap-fill the isolation trenches; and

recessing the conductive layer.

9. The method of claim 8 , wherein the recessing of the conductive layer is performed through an etch-back process or a wet etching process.

10. The method of claim 8 , wherein the conductive layer comprises a titanium nitride layer.

11. The method of claim 1 , wherein the buried bit line is electrically connected to one of the plurality of bodies through a one side contact.

12. A method for fabricating a semiconductor device, comprising:

etching a substrate comprising a buried bit line to form a plurality of pillars isolated by a trench;

forming a passivation layer gap-filling a portion of the trench;

forming spacers covering both sidewalls of the trench over the passivation layer;

forming an isolation layer gap-tilling the trench between the spacers;

selectively removing the spacers to form isolation trenches; and

forming a buried word line filling the isolation trenches after the forming the isolation layer.

13. The method of claim 12 , wherein the forming of the passivation layer comprises:

forming a dielectric layer to gap-fill the trench; and

etching back the dielectric layer.

14. The method of claim 12 , wherein the passivation layer comprises an oxide layer.

15. The method of claim 12 , wherein the isolation layer comprises an oxide layer.

16. The method of claim 12 , wherein the removing of the spacers is performed through a wet etching process.

17. The method of claim 12 , wherein the forming of the buried word line comprises:

forming a conductive layer to gap-fill the isolation trenches; and

recessing the conductive layer.

18. The method of claim 17 , wherein the recessing of the conductive layer is performed through an etch-back process or a wet etching process.

19. The method of claim 17 , wherein the conductive layer comprises a titanium nitride layer.