Semiconductor structure and method for manufacturing the same
The present invention provides a semiconductor structure, which comprises a substrate, a semiconductor base, a cavity, a gate stack, sidewall spacers, source/drain regions and a contact layer; wherein, the gate stack is located on the semiconductor base, the sidewall spacers are located on sidewalls of the gate stack, the source/drain regions are embedded within the semiconductor base and located on both sides of the gate stack, the cavity is embedded within the substrate, and the semiconductor base is suspended over the cavity, the thickness in the middle portion of the semiconductor base is greater than the thicknesses at both ends of the semiconductor base in a direction along the gate length, and both ends of the semiconductor base are connected with the substrate in a direction along the gate width; the contact layer covers exposed surfaces of the source/drain regions. Accordingly, the present invention further provides a method for manufacturing a semiconductor structure, which is favorable for reducing the contact resistance at the source/drain regions, enhancing the device performance, lowering the cost and simplifying the manufacturing process.
1. A method for manufacturing a semiconductor structure, said method comprising: (a) providing a monocrystalline substrate, forming a gate stack on the substrate, and forming sidewall spacers on sidewalls of the gate stack; (b) forming recesses in the substrates on both sides of the gate stack, and etching through the recesses on both sides of the gate stack by an anistropic wet etching to form a cavity, wherein sidewalls of the cavity are {111} crystal faces, thereby forming a semiconductor base by a portion of the substrate suspended over the cavity;(c) forming source/drain regions within the semiconductor bases on both sides of the gate stack; and (d) forming a contact layer to cover exposed surfaces of the source/drain regions.
2. The method of claim 1 , wherein the substrate is made of monocrystalline Si, monocrystalline Ge, monocrystalline SiGe or combinations thereof.
3. The method of claim 1 , wherein the crystal orientation of the substrate is <100>.
4. The method of claim 1 , wherein step (b) comprises:
forming a mask layer on the substrate and the gate stack; covering the mask layer with a photoresist layer, forming openings on the photoresist layer by exposure and development, wherein the openings are located on both sides of the gate stack; etching portions of the mask layer in the openings and removing the photoresist; and etching the substrate to form recesses on both sides of the gate stack.
5. The method of claim 4 , wherein the recesses are formed by dry etching.
6. The method of claim 1 , wherein the etching solution for the wet etching at step (b) includes KOH, TMAH, EDP or combinations thereof.
7. The method of claim 6 , wherein the etching solution for the wet etching has a concentration of about 5-40% by mass, and the temperature for the wet etching is about 40° C.-90° C.
8. The method of claim 1 , wherein forming the contact layer in step (d) comprises: forming a metal layer on exposed surfaces of the source/drain regions, wherein the metal layer is made of one of Co, Ni, Pt and Ti, or combinations thereof; annealing to enable the metal layer to react with the exposed surfaces of the source/drain regions; and removing unreacted portions of the metal layer.
9. The method of claim 8 , wherein the metal layer is formed by tilted sputtering.
10. The method of claim 1 , wherein step (c) comprises etching the sidewall spacers to expose a portion of the semiconductor base.