Area-efficient data line layouts to suppress the degradation of electrical characteristics
A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.
1. A data line layout, comprising:
a column selection line arranged in a first direction in a layer; and
a data bus line arranged in the first direction in the layer, the data bus line connected to a global I/O sense amplifier and an I/O pad, and the data bus line arranged on a cell array region, wherein a set of the column selection line and the data bus line are in parallel with each other and horizontally interposed between a pair of a bit line and a complementary bit line, and the set of the column selection line and the data bus line are formed in a first layer and the pair of bit lines is formed in a second layer.
2. The layout of claim 1 , wherein the column selection line is shared by more than two local I/O lines.
3. The layout of claim 1 , wherein the data bus line is a plurality of data bus lines,
the global I/O sense amplifier is a plurality of global I/O sense amplifiers, and
the global I/O sense amplifier is configured to be connected to a local I/O sense amplifier.
4. The layout of claim 3 , wherein the data bus lines are arranged between the global I/O sense amplifier and the I/O pad.
5. The layout of claim 3 , further comprising:
a global I/O line arranged in the first direction in the layer, the global I/O line connected between the local I/O sense amplifier and the global I/O sense amplifier.
6. The layout of claim 3 , further comprising:
a local I/O line arranged in a second direction intersecting the first direction and connected between the local I/O sense amplifier and a bit line sense amplifier,
wherein the bit line sense amplifier is connected to the bit line, the bit line crossing the cell array region.
7. The layout of claim 6 , wherein the bit line is arranged in the first direction.
8. The layout of claim 6 , wherein the local I/O line is configured to be switched in response to a column selection signal applied to the column selection line.
9. The layout of claim 8 , further comprising a global I/O line arranged in the first direction in the layer,
wherein the local I/O line is arranged in a different layer than the layer including the data bus line, the column selection line and the global I/O line.
10. The layout of claim 1 , further comprising:
a global I/O line arranged in the first direction in the layer,
wherein the layer is in the cell array region.
11. The layout of claim 10 , further comprising:
a local I/O line arranged in a second direction intersecting the first direction.
12. The layout of claim 11 , further comprising:
a word line selection line arranged in the second direction intersecting the first direction;
the bit line arranged in the first direction; and
a word line arranged in the second direction.
13. The layout of claim 1 , wherein the data bus line is less than about 14500 μm in length.
14. A semiconductor memory device configured according to the layout of claim 1 .
15. An electronic system comprising a semiconductor device configured according to the layout of claim 1 .
16. The layout of claim 1 , wherein the set further comprises a global I/O line in the first layer, the global I/O line connected between a local I/O sense amplifier and the global I/O sense amplifier.