IP Library › Granted Patent US 8,552,468
Granted Patent B2
US 8,552,468 · App. 12/724,987 · Granted Oct 8, 2013

Power semiconductor device

Inventor: Atsushi Narazaki (Chiyoda-ku, JP)
Assignee: Mitsubishi Electric Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,552,468
App. No.
12/724,987
Granted
Oct 8, 2013
Kind
B2
Abstract

A semiconductor layer has a first layer of first conductive type, a second layer of second conductive type, and a third layer. The third layer has a first region of first conductive type, and a second region of second conductive type. A second electrode is in contact with each of the first and second regions. A trench is formed on the semiconductor layer at a surface opposite to its surface facing a first electrode. A gate electrode is embedded in the trench with a gate insulating film interposed therebetween. The gate electrode includes a first portion projecting into the first layer through the first region and the second layer, a second portion projecting into the first layer through the second region and the second layer. The second portion projects into the first layer deeper than a depth in which the first portion projects into the first layer.

Claims (15)

1. A power semiconductor device, comprising:

a first electrode; and

a semiconductor layer provided on said first electrode, a trench being formed on said semiconductor layer at a surface opposite to a surface facing said first electrode,

said semiconductor layer including

a first layer of a first conductive type, provided on said first electrode,

a second layer of a second conductive type which is different from the first conductive type, provided on said first layer, and

a third layer provided on said second layer and having a first region of said first conductive type and a second region of said second conductive type,

the power semiconductor device further comprising:

a second electrode in contact with each of said first and second regions;

a gate insulating film covering an inner wall of said trench; and

a gate electrode embedded in said trench with said gate insulating film interposed therebetween,

said gate electrode including a first portion projecting into said first layer through said first region and said second layer, and a second portion projecting into said first layer through said second region and said second layer,

said second portion projecting into said first layer deeper than a depth in which said first portion projects into said first layer.

2. The power semiconductor device according to claim 1 , wherein in said trench, a portion in which said second portion of said gate electrode is embedded has a width wider than that of a portion in which said first portion of said gate electrode is embedded.

3. The power semiconductor device according to claim 1 , wherein said semiconductor layer includes a fourth layer of said second conductive type between said first electrode and said first layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2010
From: NARAZAKI, ATSUSHI
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 024090/0180 →
Priority Claims (1)
JP 2009-135022 · Jun 4, 2009 · national
Continuity (1)
Related Publication 20100308401A1 · Dec 9, 2010