IP Library Granted Patent US 8,552,475
Granted Patent B2
US 8,552,475 · App. 13/297,284 · Granted Oct 8, 2013

Apparatus of memory array using FinFETs

Inventors: Ronald Kakoschke (Munich, DE); Klaus Schruefer (Baldham, DE)
Assignee: Infineon Technologies AG
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,552,475
App. No.
13/297,284
Granted
Oct 8, 2013
Kind
B2
Abstract

One or more embodiments relate to a memory device, comprising: a memory element; and a FinFET select device including a fin, a gate line supported by the fin, and a contact element coupled between a surface of the fin and the memory element, the contact element being in direct contact with a top surface of the fin.

Claims (26)

1. A memory device, comprising:

a memory element; and

a FinFET select device including

a fin,

a gate line supported by the fin, and

a contact element coupled between a surface of the fin and the memory element, the contact element being in direct contact with a top surface of the fin.

2. The memory device of claim 1 , wherein the contact element directly contacts a sidewall surface of the fin.

3. The memory device of claim 1 , wherein the memory element is a NVM.

4. The memory device of claim 3 , wherein the memory element is selected from a group of memory elements consisting of PCRAM, MRAM, CBRAM, and FeRAM.

5. The memory device array of claim 4 , wherein said PCRAM memory element comprises a chalcogenide memory material.

6. The memory device of claim 1 , wherein said contact element comprises one or more materials selected from the group consisting of tungsten, copper, silver, gold, aluminum, and alloys thereof.

7. The memory device of claim 1 , wherein the contact element at least partially wraps around the fin.

8. A FinFET device, comprising:

a fin;

a gate line supported by the fin; and

a contact element in direct contact with a top surface of the fin.

9. The device of claim 8 , wherein the contact element directly contacts a sidewall surface of the fin.

10. The device of claim 8 , wherein the contact element comprises one or more materials selected from the group consisting of tungsten, copper, silver, gold, aluminum, and alloys thereof.

11. The device of claim 8 , wherein the contact element at least partially wraps around the fin.

12. A FinFET device, comprising:

a fin; and

a contact element in direct contact with a top surface of a source/drain region of the fin.

13. The device of claim 12 , wherein the contact element directly contact a sidewall surface of the fin.

14. The device of claim 12 , wherein the contact element comprises one or more materials selected from the group consisting of tungsten, copper, silver, gold, aluminum, and alloys thereof.

15. The device of claim 12 , wherein the source/drain region is a drain region.

16. The device of claim 12 , wherein the contact element at least partially wraps around the fin.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 71984 FRAME: 618. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 19, 2025
From: INFINEON TECHNOLOGIES AG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 072496/0759 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2025
From: INFINEON TECHNOLOGIES AG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 071984/0618 →
Continuity (3)
Continuation 12784524 · May 21, 2010
Continuation 11734069 · Apr 11, 2007
Related Publication 20120068149A1 · Mar 22, 2012