Corner transistor and method of fabricating the same
A method of fabricating a corner transistor is described. An isolation structure is formed in a substrate to define an active region. A treating process is performed to make the substrate in the active region have sharp corners at top edges thereof. The substrate in the active region is covered by a gate dielectric layer. A gate conductor is formed over the gate dielectric layer. A source region and a drain region are formed in the substrate beside the gate conductor.
1. A method of fabricating a corner transistor, comprising:
forming an isolation structure in a substrate to define an active area;
performing a treating process to make the substrate in the active area have sharp corners at top edges thereof;
covering the substrate in the active area by a gate dielectric layer;
forming a gate conductor over the gate dielectric layer; and
forming a source region and a drain region in the substrate beside the gate conductor, wherein a top surface of the gate conductor is lower than a top surface of the source region and a top surface of the drain region.
2. The method of claim 1 , wherein the treating process comprises:
making a top surface of the substrate in the active area have a curved shape.
3. The method of claim 1 , wherein the treating process comprises:
performing a thermal oxidation process to oxidize a surface of the substrate in the active area and form an oxide layer with a curved profile; and
removing the oxide layer and a portion of the isolation structure so that the surface of the substrate in the active area and the sharp corners are protrudent over a surface of the remaining isolation structure.
4. The method of claim 3 , wherein the gate dielectric layer also covers the sharp corners.
5. The method of claim 3 , wherein the treating process further comprises:
performing a first etching process to remove a portion of the substrate in the active area, such that a surface of the remaining substrate in the active area is lower than the surface of the remaining isolation structure and a trench is formed thereby.
6. The method of claim 5 , wherein the first etching process comprises an anisotropic etching process.
7. The method of claim 5 , wherein the treating process further comprises:
performing a second etching process to remove a portion of the isolation structure at sidewalls of the trench so that the surface of the remaining substrate in the active area and the sharp corners are protrudent over a bottom of the trench.
8. The method of claim 7 , wherein the second etching process comprises an isotropic etching process.
9. The method of claim 7 , wherein the gate dielectric layer also covers the sharp corners.
10. The method of claim 1 , wherein the treating process comprises:
performing a first etching process to remove a portion of the substrate in the active area, such that a surface of the remaining substrate in the active area is lower than a surface of the isolation structure and a trench is formed thereby.
11. The method of claim 10 , wherein the first etching process comprises an anisotropic etching process.
12. The method of claim 10 , wherein the treating process further comprises:
performing a second etching process to remove a portion of the isolation structure at sidewalls of the trench so that the surface of the remaining substrate in the active area and the sharp corners are protrudent over a bottom of the trench.
13. The method of claim 12 , wherein the second etching process comprises an isotropic etching process.
14. The method of claim 12 , wherein the gate dielectric layer also covers the sharp corners.
15. A corner transistor, comprising:
a substrate, having therein an isolation structure defining an active area, wherein the substrate in the active area have sharp corners at two edges thereof;
a gate dielectric layer, covering the substrate in the active area;
a gate conductor over the gate dielectric layer; and
a source region and a drain region in the substrate beside the gate conductor, wherein a top surface of the gate conductor is lower than a top surface of the source region and a top surface of the drain region.
16. The corner transistor of claim 15 , wherein a top surface of the substrate in the active area and the sharp corners are protrudent over a surface of the isolation structure.
17. The corner transistor of claim 15 , wherein a top surface of the substrate in the active area is lower than a top surface of the isolation structure so that a trench is formed exposing the top surface of the substrate in the active area.
18. The corner transistor of claim 15 , wherein a top surface of the substrate in the active area is lower than a top surface of the isolation structure so that a trench is formed, and the surface of the substrate in the active area and the sharp corners are protrudent over a bottom of the trench.
19. The corner transistor of claim 18 , wherein the gate dielectric layer also covers the sharp corners.
20. The corner transistor of claim 15 , wherein a top surface of the substrate in the active area has a curved shape.