Apparatus and method for dynamically dampening a transient step response
A circuit has a digital to analog (DA) resistance ladder having an analog output; a capacitor coupled to the analog output; a first resistance coupled from the capacitor to ground; and a switch coupled to the capacitor in parallel to the resistor, wherein the switch, when closed, has a second resistance, and the first resistance is greater than the second resistance.
1. A circuit, comprising:
a digital to analog (DA) resistance ladder having an analog output;
a capacitor coupled to the analog output;
a first resistance coupled from the capacitor to ground;
a switch coupled to the capacitor in parallel to the resistor, wherein the switch, when closed, has a second resistance, and the first resistance is greater than the second resistance.
2. The circuit of claim 1 , wherein the DA resistance ladder comprises a resistance of a first ladder value denoting a least significant bit, and a resistance of a second ladder value denoting a most significant bit.
3. The circuit of claim 1 , wherein the switch is a NFET.
4. The circuit of claim 1 , wherein a logic is coupled to a driver of the switch and the DA resistance ladder.
5. The circuit of claim 1 , wherein the digital to analog ladder has a plurality of ladder switches that are controlled by a logic to convert a digital value to an analog output voltage at the analog output.
6. The circuit of claim 5 , wherein the logic:
a) closes the switch upon a transition of at least one ladder switch of the plurality of ladder switches; and
b) opens the switch after a transition of a ladder switch of the plurality of ladder switches.
7. The circuit of claim 1 , wherein the capacitor is replaceable with a second capacitor, wherein the capacitor is outside of an integrated circuit that contains the first resistance and the switch.
8. A system, comprising:
an analog output;
a capacitor coupled to the analog output ;
a first resistance coupled from the node to ground;
a switch coupled to the node in parallel to the resistor,
wherein the switch, when closed, has a second resistance, and the first resistance is greater than the second resistance;
a driver coupled to a gate of the switch; and
a logic coupled to the driver, wherein the logic directs the driver to:
a) close the switch to mitigate a transient in the analog output, and
b) open the switch after the transient has occurred.
9. The system of claim 8 , further comprising a digital to analog (DA) ladder coupled to the driver and the analog output, wherein the DA ladder comprises a resistance of a first value denoting a least significant bit, and a resistance of a second value denoting a most significant bit.
10. The system of claim 9 , further comprising a voltage source and a voltage sink coupled to the DA ladder, wherein an analog signal of the analog signal output is a voltage value between the a voltage of the voltage source and a voltage of the voltage sink.
11. The system of claim 8 , wherein a time constant of a the capacitor and the first resistance is substantially at least one order of magnitude greater than a time constant of a decay of the transient of the output voltage.
12. The system of claim 8 , wherein the capacitor is replaceable with a second capacitor having a different capacitance.
13. The system of claim 8 , wherein the capacitor is outside of an integrated circuit that contains the first resistance and the switch.
14. The system of claim 8 , wherein the logic closes the switch upon a transition from a first output voltage to a second output voltage on an output node coupled to the capacitor.
15. The system of claim 14 , wherein the logic:
a) closes the switch upon a transition of at least one ladder switch of the plurality of ladder switches; and
b) opens the switch after a transition of a ladder switch of the plurality of ladder switches.
16. A method, comprising:
trickle charging a capacitor through a series resistor;
transitioning a voltage at a output node coupled to the capacitor;
closing a switch if a dampening of a transient is needed;
shorting the series resistor by closing the switch; and
mitigating the transient through employment of the capacitor.
17. The method of claim 16 , wherein the switch remain open if it is determined that a dampening is not occurring on the output node.
18. The method of claim 16 , further comprising employing a digital to analog converter to change the voltage on the output node.
19. The method of claim 16 , further comprising charging the capacitor by the transient if the capacitor is not fully charged by the trickle charge.
20. The method of claim 19 , further comprising opening the switch after the transient is finished.