Methods for fabricating integrated circuits

1. A method for fabricating an integrated circuit comprising:

etching trenches into a silicon substrate and filling the trenches with an insulating material to separate spaced apart silicon fins having top surfaces and sidewalls;

forming dummy gate structures overlying and transverse to the fins, the dummy gate structures overlying first regions of the fins;

filling between the dummy gate structures with a back fill material, the back fill material overlying second regions of the fins;

removing the dummy gate structures to expose the top surfaces of the first regions of the fins;

etching the insulating material to expose the sidewalls of the first regions of the fins;

depositing a high-k dielectric material and a work function determining gate electrode material overlying the top surfaces and sidewalls of the first regions of the fins;

removing the back fill material to expose the top surfaces of the fins in the second regions;

forming metal silicide contacts on the top surfaces of the second regions of the fins;

forming conductive contacts to the work function determining material and to the metal silicide contacts;

etching the top surfaces of the first regions of the fins exposed by removing the dummy gate structures to form recesses; and

epitaxially growing a layer of undoped silicon to fill the recesses.

2. The method of claim 1 further comprising epitaxially growing a layer of undoped silicon over the top surfaces of the fins.

3. The method of claim 1 further comprising providing a bulk silicon substrate, wherein etching trenches into a silicon substrate comprises etching trenches into the bulk silicon substrate.

4. The method of claim 1 wherein removing the back fill material comprises:

depositing a layer of spin on glass;

planarizing the layer of spin on glass to leave a portion of the spin on glass overlying the work function determining gate electrode material; and

etching the back fill material using the spin on glass as an etch mask.

5. The method of claim 1 wherein forming metal silicide contacts comprises forming nickel silicide contacts and wherein forming conductive contacts comprises depositing and planarizing a metal on both the metal silicide contacts and on the work function determining gate electrode material.

6. The method of claim 1 further comprising epitaxially growing a layer of undoped silicon on the top surfaces of the fins to form undoped regions of the fins before filling between the dummy gate structures with a back fill material.

7. The method of claim 1 further comprising epitaxially growing a layer of undoped silicon on the top surfaces of the fins to form undoped regions of the fins before removing the dummy gate structures.

8. The method of claim 1 wherein removing the back fill material comprises removing the back fill material after depositing a high-k dielectric material and a work function determining gate electrode material.

9. The method of claim 1 wherein forming dummy gate structures overlying and transverse to the fins comprises:

forming dummy gate layers overlying the fins; and

patterning the dummy gate layers to form dummy gate stacks.

10. A method for fabricating an integrated circuit comprising:

etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins;

epitaxially growing a layer of undoped silicon to form an upper, undoped region of the fins;

forming dummy gate structures overlying and transverse to the plurality of fins;

filling between the dummy gate structures with a back fill material;

removing the dummy gate structures to expose a portion of the fins;

depositing a high-k dielectric material and a work function determining gate electrode material overlying the portion of the fins;

removing the back fill material to expose a second portion of the fins;

forming metal silicide contacts on the second portion of the fins; and

forming conductive contacts to the work function determining material and to the metal silicide, wherein forming dummy gate structures comprises:

forming a layer of insulator overlying the fins;

depositing a layer of silicon germanium overlying the layer of insulator;

depositing a layer of hard mask material overlying the layer of silicon germanium;

patterning the layer of hard mask material, layer of silicon germanium, and layer of insulator to form dummy gate stacks; and

forming sidewall spacers on the dummy gate stacks.

11. The method of claim 10 further comprising:

etching trenches into the plurality of fins using the dummy gate stacks and sidewall spacers as an etch mask;

filling the trenches by a process of selective epitaxial growth of a material selected from the group consisting of silicon germanium and silicon carbon.

12. The method of claim 10 wherein filling between dummy gate structures comprises:

depositing silicon between adjacent ones of the plurality of dummy gate structures; and

planarizing the silicon by chemical mechanical planarization.

13. A method for fabricating an integrated circuit comprising:

etching trenches into a semiconductor substrate to define sidewalls of spaced apart semiconductor fins having top surfaces;

filling the trenches with an insulating material such that the insulating material is planar with the top surfaces of the fins;

forming dummy gate structures overlying the insulating material and first regions of the fins, wherein second regions of the fins are defined between the dummy gate structures;

covering the second regions of the fins with a fill material;

removing the dummy gate structures to expose the top surfaces of the first regions of the fins;

etching the insulating material to expose the sidewalls of the first regions of the fins;

forming a gate structure overlying the top surfaces and sidewalls of the first regions of the fins;

removing the fill material to expose the top surfaces of the fins in the second regions;

forming contacts on the top surfaces of the second regions of the fins;

wherein forming dummy gate structures comprises:

forming a layer of insulator overlying the fins and the insulating material;

depositing a layer of silicon germanium overlying the layer of insulator;

depositing a layer of hard mask material overlying the layer of silicon germanium;

patterning the layer of hard mask material, layer of silicon germanium, and layer of insulator to form dummy gate stacks; and

forming sidewall spacers on the dummy gate stacks.

14. The method of claim 13 further comprising providing a bulk silicon substrate, wherein etching trenches into a semiconductor substrate comprises etching trenches into the bulk silicon substrate.

15. The method of claim 13 further comprising epitaxially growing a layer of undoped silicon over the top surfaces of the fins.

16. The method of claim 13 further comprising:

etching the top surfaces of the first regions of the fins exposed by removing the dummy gate structures to form recesses; and

epitaxially growing a layer of undoped silicon to fill the recesses.

17. The method of claim 13 further comprising:

etching stress-inducing trenches into the second regions of the fins between the dummy gate structures; and

growing epitaxial material in the stress-inducing trenches, wherein covering the second regions of the fins with a fill material comprises depositing the fill material over the epitaxial material in the stress-inducing trenches.

18. The method of claim 13 further comprising:

removing the dummy gate structures to expose the top surfaces of the first regions of the fins;

etching the first regions of the fins to form channel trenches; and

growing channel epitaxial material in the channel trenches, wherein forming a gate structure comprises forming a gate structure overlying the channel epitaxial material and sidewalls of the first regions of the fins.