IP Library Granted Patent US 8,557,706
Granted Patent B2
US 8,557,706 · App. 13/332,170 · Granted Oct 15, 2013

Substrate processing method

Inventors: Masanobu Honda (Nirasaki, JP); Hironobu Ichikawa (Nirasaki, JP)
Assignee: Tokyo Electron Limited
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Quick Facts
Patent No.
US 8,557,706
App. No.
13/332,170
Granted
Oct 15, 2013
Kind
B2
Abstract

A substrate processing method that forms an opening, which has a size that fills the need for downsizing a semiconductor device and is to be transferred to an amorphous carbon film, in a photoresist film of a substrate to be processed. Deposit is accumulated on a side wall surface of the opening in the photoresist film using plasma produced from a deposition gas having a gas attachment coefficient S of 0.1 to 1.0 so as to reduce the opening width of the opening.

Claims (13)

1. A substrate processing method that processes a substrate in which a to-be-processed layer, an intermediate layer, and a mask layer are stacked in this order, and in which the mask layer has an opening to which part of the intermediate layer is exposed, comprising:

an opening width reducing step comprising accumulating deposit on a side wall surface of the opening in the mask layer using plasma produced from a deposition gas alone having a gas attachment coefficient S of 0.1 to 1.0, thus reducing an opening width of the opening, and

an intermediate layer etching step of transferring the opening, the opening width of which is reduced in said opening width reducing step, onto the intermediate layer using plasma produced from a mixed gas comprising the deposition gas and an etching gas,

wherein in said intermediate layer etching step, no bias electric power is applied to the substrate.

2. A substrate processing method as claimed in claim 1 , wherein the deposition gas is represented by a general expression, C x H y F Z (x, y, and z are 0 or positive integers).

3. A substrate processing method as claimed in claim 2 , wherein the deposition gas is CHF 3 gas.

4. A substrate processing method as claimed in claim 1 , wherein in said opening width reducing step, bias electrical power of 100 W to 500 W is applied to the substrate.

5. A substrate processing method as claimed in claim 1 , wherein a processing time in said opening width reducing step is 0.5 minute to 3 minutes.

6. A substrate processing method as claimed in claim 1 , wherein said opening width reducing step comprises converging the opening width of the opening in the mask layer to a predetermined value corresponding to a value of the gas attachment coefficient S of the deposition gas.

7. A substrate processing method as claimed in claim 1 , wherein said opening width reducing step comprises reducing the opening width of the opening in the mask layer, and smoothing out variations in the opening widths of the openings formed in the mask layer to reduce deviations.

8. A substrate processing method as claimed in claim 1 , further comprising:

a to-be-processed layer etching step of transferring the opening transferred to the intermediate layer in said intermediate layer etching step onto the to-be-processed layer using plasma produced from a non-deposition gas.

9. A substrate processing method as claimed in claim 1 , wherein in said opening width reducing step, the side wall of the opening is made to be tapered.

Priority Claims (2)
JP 2008-181729 · Jul 11, 2008 · national
JP 2009-026127 · Feb 6, 2009 · national
Continuity (3)
Division 12493667 · Jun 29, 2009
Provisional Application 61092619 · Aug 28, 2008
Related Publication 20120094495A1 · Apr 19, 2012