IP Library › Granted Patent US 8,558,372
Granted Patent B2
US 8,558,372 · App. 13/584,022 · Granted Oct 15, 2013

Semiconductor device

Inventor: Syuji Negoro (Nagano, JP)
Assignee: Shinko Electric Industry Co., Ltd.
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Quick Facts
Patent No.
US 8,558,372
App. No.
13/584,022
Granted
Oct 15, 2013
Kind
B2
Abstract

A semiconductor device includes a wiring substrate, a first semiconductor chip mounted on the wiring substrate, and a second semiconductor chip mounted on the wiring substrate. The second semiconductor chip generates less heat than the first semiconductor chip. A heat dissipation plate is arranged on the wiring substrate and partially at a higher location than the first and second semiconductor chips. The heat dissipation plate is connected to the first semiconductor chip and includes an opening formed at a location corresponding to an upper surface of the second semiconductor chip. The upper surface of the second semiconductor chip is entirely exposed from the heat dissipation plate through the opening.

Claims (23)

1. A semiconductor device comprising:

a wiring substrate;

a first semiconductor chip mounted on the wiring substrate;

a second semiconductor chip mounted on the wiring substrate, wherein the second semiconductor chip generates less heat than the first semiconductor chip; and

a heat dissipation plate arranged on the wiring substrate and partially at a higher location than the first semiconductor chip and the second semiconductor chip, wherein

the heat dissipation plate is connected to the first semiconductor chip,

the heat dissipation plate includes an opening formed at a location corresponding to an upper surface of the second semiconductor chip, and

the upper surface of the second semiconductor chip is entirely exposed from the heat dissipation plate through the opening.

2. The semiconductor device according to claim 1 , wherein the second semiconductor chip is put in the opening, and the semiconductor device further comprises a thermal insulation resin formed between the second semiconductor chip and a wall defining the opening.

3. The semiconductor device according to claim 1 , further comprising a thermal insulation resin arranged on the wiring substrate between the first semiconductor chip and the second semiconductor chip.

4. The semiconductor device according to claim 2 , further comprising a thermal insulation resin arranged on the wiring substrate between the first semiconductor chip and the second semiconductor chip.

5. The semiconductor device according to claim 1 , wherein the second semiconductor chip is free from contact with a wall defining the opening.

6. The semiconductor device according to claim 5 , wherein an air passage is formed between the second semiconductor chip and the wall defining the opening.

7. The semiconductor device according to claim 5 , wherein a thermal insulation resin is formed between the second semiconductor chip and the wall defining the opening.

8. The semiconductor device according to claim 1 , further comprising a heat dissipation portion arranged on the heat dissipation plate and connected to the heat dissipation plate and the second semiconductor chip.

9. A semiconductor device comprising:

a wiring substrate;

a first semiconductor chip mounted on the wiring substrate;

a second semiconductor chip mounted on the wiring substrate, wherein the second semiconductor chip generates less heat than the first semiconductor chip;

a first heat dissipation plate arranged on the wiring substrate and partially at a higher location than the first semiconductor chip and the second semiconductor chip, wherein the first heat dissipation plate is connected to the first semiconductor chip and includes an opening formed at a location corresponding to an upper surface of the second semiconductor chip;

a second heat dissipation plate arranged in the opening and connected to the second semiconductor chip; and

a thermal insulation resin formed between the second heat dissipation plate and a wall defining the opening.

10. The semiconductor device according to claim 9 , wherein the thermal insulation resin is arranged on the wiring substrate between the first semiconductor chip and the second semiconductor chip.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2012
From: NEGORO, SYUJI
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 028775/0614 →
Priority Claims (1)
JP 2011-178933 · Aug 18, 2011 · national
Continuity (1)
Related Publication 20130043581A1 · Feb 21, 2013