IP Library › Granted Patent US 8,558,497
Granted Patent B2
US 8,558,497 · App. 13/227,149 · Granted Oct 15, 2013

Reduced electromagnetic interference for pulse-width modulation

Inventor: David G. Wright (San Diego, CA)
Assignee: Cypress Semiconductor Corporation
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Quick Facts
Patent No.
US 8,558,497
App. No.
13/227,149
Granted
Oct 15, 2013
Kind
B2
Abstract

A method and apparatus to drive a load using a pulse-width modulated (PWM) signal and spread a spectrum of the PWM signal across a plurality of frequencies while maintaining a constant duty cycle for the load.

Claims (55)

1. A method, comprising:

driving a load using a pulse-width modulated (PWM) signal; and

spreading, by a processing device, a spectrum of the PWM signal across a plurality of frequencies while maintaining a substantially constant duty cycle for the load, wherein the spreading comprises varying a clock frequency for the PWM signal according to a spreading profile and synchronizing the variations in the clock frequency with a change in a period of the PWM signal.

2. The method of claim 1 , wherein the spreading comprises:

maintaining a constant clock frequency for the PWM signal; and

varying a period length of the PWM signal according to a spreading profile.

3. The method of claim 2 , wherein varying the period length comprises:

determining a terminal count value representing the period length; and

calculating a duty cycle count value corresponding to the substantially constant duty cycle for the load.

4. The method of claim 2 , wherein the spreading profile comprises one of a triangle profile, a “Hershey kiss” profile, and a pseudo-random profile.

5. The method of claim 1 , wherein synchronizing the variations comprises:

generating a first clock frequency and a second clock frequency;

identifying a change in the period of the PWM signal; and

switching from the first clock frequency to the second clock frequency at the change in the period.

6. The method of claim 1 , wherein the spreading comprises:

varying a clock frequency for the PWM signal according to a first spreading profile;

synchronizing the variations in the clock frequency with a change in a period of the PWM signal; and

varying a period length of the PWM signal according to a second spreading profile.

7. The method of claim 1 , wherein the load comprises a brushless direct current (BLDC) motor.

8. The method of claim 1 , wherein the load comprises a motor using field oriented control (FOC).

9. An apparatus, comprising:

a pulse-width modulation (PWM) circuit configured to drive a load using a PWM signal; and

a PWM control circuit, coupled to the PWM circuit, configured to spread a spectrum of the PWM signal across a plurality of frequencies while maintaining a desired duty cycle for the load, the PWM control circuit comprising a selection circuit to vary a clock frequency for the PWM signal according to a spreading profile and synchronize the variations in the clock frequency with a change in a period of the PWM signal.

10. The apparatus of claim 9 , wherein the PWM circuit comprises:

a counter clocked by a clock signal;

a first digital comparator to compare a value of the counter to a duty cycle count value;

a second digital comparator to compare the value of the counter to a terminal count value; and

a flip flop configured to switch an output of the PWM circuit based on outputs of the first and second digital comparators.

11. The apparatus of claim 10 , wherein the PWM control circuit comprises:

a processing device;

a storage device, coupled to the processing device, to store a plurality of terminal count values, the plurality of terminal count values to vary a period length of the PWM signal according to a spreading profile while the clock signal remains constant.

12. The apparatus of claim 11 , the processing device to calculate a plurality of duty cycle count values corresponding to the plurality of terminal count values based on the desired duty cycle.

13. The apparatus of claim 10 , further comprising:

a substantially constant-frequency clock source; and

a plurality of clock multipliers coupled to the substantially constant-frequency clock source to provide varying clock frequencies,

wherein the selection circuit to select an output of one of the plurality of clock multipliers to provide as the clock signal.

14. The apparatus of claim 10 , further comprising:

a programmable clock generator, wherein an output of the programmable clock generator is provided as the clock signal, and wherein a change in the output of the programmable clock generator is synchronized with a change in a period of the PWM signal.

15. The apparatus of claim 9 , wherein the load comprises a motor.

16. The apparatus of claim 9 , wherein the load comprises a brushless direct current (BLDC) motor.

17. The apparatus of claim 9 , wherein the load comprises a motor using field oriented control (FOC).

18. A method comprising:

comparing a value of a counter to a duty cycle count register value, wherein the counter is clocked by a clock signal;

varying a frequency of the clock signal and synchronizing the variations in the clock frequency with a change in a PWM period according to a spreading profile;

if the value of the counter equals the duty cycle count register value, switching an output of a pulse-width modulation (PWM) circuit used to drive a load from a first state to a second state;

comparing the value of the counter to a terminal count register value;

if the value of the counter equals the terminal count value, switching the output of the PWM circuit from the second state to the first state.

19. The method of claim 18 further comprising:

if the value of the counter equals the terminal count value:

resetting the counter to an initial value; and

loading a subsequent duty cycle count value into the duty cycle register and a subsequent terminal count value into the terminal count register.

20. The method of claim 19 , wherein the subsequent terminal count value varies a length of the PWM period according to the spreading profile.

21. The method of claim 19 , wherein the subsequent duty cycle count value is proportional to the subsequent terminal count value to maintain a substantially constant duty cycle.

22. The method of claim 18 , wherein the load comprises a brushless direct current (BLDC) motor.

23. The method of claim 18 , wherein the load comprises a motor using field oriented control (FOC).

Assignments (6)
MERGER Recorded Nov 14, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073571/0456 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2011
From: WRIGHT, DAVID G.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 026867/0978 →
Continuity (2)
Provisional Application 61508235 · Jul 15, 2011
Related Publication 20130015798A1 · Jan 17, 2013