Compensated current cell to scale switching glitches in digital to analog convertors
Compensated current cell to scale switching glitches in digital to analog convertors. A compensated current cell is disclosed that includes first and second switching transistors configured to switch an input current between first and second outputs based on first and second input signals, respectively, a first compensation transistor connected to the first input signal to provide a first compensation current that is connected to the second output, and a second compensation transistor connected to the second input signal to provide a second compensation current that is connected to the first output, the first and second compensation transistors having source terminals that are connected together. In another aspect, switching glitches are scaled based on a size difference between the switching transistors and the compensation transistors.
1. A compensated current cell, the cell comprising:
first and second switching transistors configured to switch an input current between first and second outputs based on first and second input signals, respectively;
a first compensation transistor connected to the first input signal to provide a first compensation current that is connected to the second output, the first compensation current based on the second input signal; and
a second compensation transistor connected to the second input signal to provide a second compensation current that is connected to the first output, the second compensation current based on the first signal, the first and second compensation transistors having source terminals that are connected together.
2. The cell of claim 1 , the first and second switching transistors and the first and second compensation transistors are MOS transistors.
3. The cell of claim 1 , the first compensation current configured to scale glitches on second output and the second compensation current configured to scale glitches on first output.
4. The cell of claim 3 , the glitches on the first output are scaled based on a size difference between the first switching transistor and the second compensation transistor.
5. The cell of claim 4 , the size difference between the first switching transistor and the second compensation transistor is set equal to a current scaling factor.
6. The cell of claim 5 , the current scaling factor is set to zero to reduce the glitches on the first output.
7. The cell of claim 3 , the glitches on the second output are scaled based on a size difference between the second switching transistor and the first compensation transistor.
8. The cell of claim 7 , the size difference between the second switching transistor and the first compensation transistor is set equal to a current scaling factor.
9. The cell of claim 8 , the current scaling factor is set to zero to reduce the glitches on the second output.
10. A compensated current cell, the cell comprising:
first means for switching an input current to a first output based on a first input signal;
second means for switching the input current to a second output based on a second input signal;
first means for generating a first compensation current in response to the first input signal, the first compensation current is coupled to the second output, the first compensation current based on the second input signal; and
second means for generating a second compensation current in response to the second input signal, the second compensation current is coupled to the first output, the second compensation current based on the first input signal, the second means for generating connected to the first means for generating.
11. The cell of claim 10 , the first compensation current is configured to scale glitches on the second output and the second compensation current is configured to scale glitches on the first output.
12. The cell of claim 11 , the glitches on the first output are scaled based on a first size difference between the first means for switching and the second means for generating and the glitches on the second output are scaled based on a second size difference between the second means for switching and the first means for generating.
13. The cell of claim 12 , the first size difference and the second size difference are set equal to a current scaling factor.
14. The cell of claim 13 , the current scaling factor is set to zero to reduce the glitches on the first and second outputs.
15. A digital to analog convertor (DAC), comprising:
at least one compensated current cells configured to receive a digital input and generate a current output, each compensated current cell comprising:
first and second switching transistors configured to switch an input current between first and second outputs based on first and second input signals, respectively;
a first compensation transistor connected to the first input signal to provide a first compensation current that is connected to the second output; and
a second compensation transistor connected to the second input signal to provide a second compensation current that is connected to the first output, the first and second compensation transistors having source terminals that are connected together.
16. The cell of claim 15 , the first and second switching transistors and the first and second compensation transistors are MOS transistors.
17. The DAC of claim 15 , glitches on the first output are scaled based on a first size difference between the first switching transistor and the second compensation transistor and glitches on the second output are scaled based on a second size difference between the second switching transistor and the first compensation transistor.
18. The DAC of claim 16 , the first size difference and the second size difference are set equal to a current scaling factor.
19. The DAC of claim 17 , the current scaling factor is set to scale the glitches on the first and second output.
20. The DAC of claim 19 , the current scaling factor is set to zero to reduce the glitches on the first and second output.