Array substrate for liquid crystal display device, liquid crystal display device and method of fabricating the same

1. An array substrate for a liquid crystal display device, comprising:

a gate line on a substrate including a display region and a non-display region at a periphery of the display region;

a common line on the substrate;

a data drive integrated circuit in the non-display region;

first and second data lines crossing the gate line to define a pixel region in the display region, the first and second data lines having a difference in a distance from the data drive integrated circuit;

first and second data link lines connected to the data drive integrated circuit, the first and second data link lines respectively connected to the first and second data lines;

a thin film transistor in the pixel region connected to the gate line and one of the first and second data lines;

a pixel electrode in the pixel region and connected to the thin film transistor; and

a first conductive pattern in the non-display region and connected to the common line such that a common voltage is applied to the first conductive pattern, the first conductive pattern overlapping the first and second data link lines to form first and second capacitors, respectively.

2. The substrate according to claim 1 , further comprising a common electrode including a plurality of common branches connected to the common line, wherein the pixel electrode includes a plurality of pixel branches alternately arranged with the common branches, and the common electrode is connected to the common line.

3. The substrate according to claim 1 , wherein the second data line is closer to the data drive integrated circuit than the first data line, and a capacitance of the second capacitor is larger than that of the first capacitor.

4. The substrate according to claim 1 , wherein the first conductive pattern has a triangle shape.

5. The substrate according to claim 1 , wherein each of the first and second data link lines has a zigzag shape, and a number of the zigzag shape of the first data link line is greater than that of the zigzag shape of the second data link line.

6. The substrate according to claim 1 , further comprising a connection part extending from the first conductive pattern and contacting the common line.

7. The substrate according to claim 6 , further comprising:

a gate insulating layer on the gate line and the common line; and

a passivation layer on the first and second data lines and the first and second data link lines,

wherein the passivation layer and the gate insulating layer has a contact hole exposing the common line, and the connection part on the passivation layer contacts the common line through the contact hole.

8. The substrate according to claim 1 , further comprising:

a gate drive integrated circuit in the non-display region;

first and second gate link lines connected to the gate drive integrated circuit; and

a second conductive pattern in the non-display region and connected to the common line such that a common voltage is applied to the second conductive pattern, the second conductive pattern overlapping the first and second gate link lines to form third and fourth capacitors, respectively,

wherein the gate line includes first and second gate lines respectively connected to the first and second gate link lines.

9. The substrate according to claim 8 , wherein the second gate line is closer to the gate drive integrated circuit than the first gate line, and a capacitance of the fourth capacitor is larger than that of the third capacitor.

10. The substrate according to claim 1 , wherein the pixel electrode has a plate shape covering the pixel region.

11. A method of fabricating an array substrate for a liquid crystal display device, comprising:

forming a gate line and a common line on a substrate including a display region and a non-display region at a periphery of the display region;

forming first and second data lines and first and second data link lines, the first and second data line crossing the gate line to define a pixel region in the display region, the first and second data link lines respectively connected to the first and second data lines;

forming a thin film transistor in the pixel region and connected to the gate line and one of the first and second data lines;

forming a pixel electrode and a first conductive pattern, the pixel electrode in the pixel region and connected to the thin film transistor, the first conductive pattern in the non-display region and connected to the common line such that a common voltage is applied to the first conductive pattern, the first conductive pattern overlapping the first and second data link lines to form first and second capacitors, respectively; and

forming a data drive integrated circuit in the non-display region and connected to each of the first and second data link lines,

wherein the first and second data lines have a difference in a distance from the data drive integrated circuit.

12. The method according to claim 11 , further comprising forming a common electrode including a plurality of common branches connected to the common line, wherein the pixel electrode includes a plurality of pixel branches alternately arranged with the common branches, and the common electrode is connected to the common line.

13. The method according to claim 11 , wherein the second data line is closer to the data drive integrated circuit than the first data line, and a capacitance of the second capacitor is larger than that of the first capacitor.

14. The method according to claim 11 , wherein the first conductive pattern has a triangle shape.

15. The method according to claim 11 , wherein each of the first and second data link lines has a zigzag shape, and a number of the zigzag shape of the first data link line is greater than that of the zigzag shape of the second data link line.

16. The method according to claim 11 , further comprising forming a connection part extending from the first conductive pattern and contacting the common line.

17. The method according to claim 16 , further comprising:

forming a gate insulating layer on the gate line and the common line;

forming a passivation layer on the first and second data lines and the first and second data link lines; and

forming a contact hole through the passivation layer and the gate insulating layer to expose the common line,

wherein the connection part on the passivation layer contacts the common line through the contact hole.

18. The method according to claim 11 , further comprising:

forming first and second gate link lines;

forming a second conductive pattern in the non-display region and connected to the common line such that a common voltage is applied to the second conductive pattern, the second conductive pattern overlapping the first and second gate link lines to form third and fourth capacitors, respectively; and

forming a gate drive integrated circuit in the non-display region and connected to each of the first and second gate link lines,

wherein the gate line includes first and second gate lines respectively connected to the gate link lines.

19. The method according to claim 18 , wherein the second gate line is closer to the gate drive integrated circuit than the first gate line, and a capacitance of the fourth capacitor is larger than that of the third capacitor.

20. The method according to claim 11 , wherein the pixel electrode has a plate shape covering the pixel region.

21. The substrate according to claim 1 , wherein the first conductive pattern is disposed in the non-display region comprising a triangle shape, wherein each of the first and second data link lines are disposed in the non-display region comprising a zigzag shape overlapping the first conductive pattern to form the first and second capacitors, and wherein a number of the zigzag shape of the first data link line is greater than that of the zigzag shape of the second data link line.

22. The method according to claim 11 , wherein the first conductive pattern is disposed in the non-display region comprising a triangle shape, wherein each of the first and second data link lines are disposed in the non-display region comprising a zigzag shape overlapping the first conductive pattern to form the first and second capacitors, and wherein a number of the zigzag shape of the first data link line is greater than that of the zigzag shape of the second data link line.