Method of driving a gate line and gate drive circuit for performing the method
A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal.
1. A method of driving a gate line of a device including a shift register, the method comprising:
maintaining, at a current stage (m), a first node signal at a high level based on one of a previous stage of a vertical start signal;
outputting a clock signal as a gate signal provided to the gate line in response to the first node signal in a high state;
maintaining the first node signal at a ground voltage by a first node holding part responsive to a clock signal of a stage two stages (m+2) beyond the current stage;
maintaining the gate signal at the ground voltage by a gate holding part responsive to a clock signal of a stage three stages (m+3) beyond the current stage; and
maintaining the gate signal at the ground voltage by a pull-down part responsive to a gate signal of the next stage or the vertical start signal,
wherein the clock signal of the stage three stages (m+3) beyond the current stage is delayed by about ¾ period of the current stage (m) clock signal.
2. The method of claim 1 , further comprising deactivating the gate signal when an output enable signal which activates the gate signal of the next stage is high.
3. A gate drive circuit in which a plurality of stages are connected in series, the date drive circuit sequentially activating a plurality of gate lines, a present stage (m) comprising:
a buffer part providing a first node with a signal having a high level based on one of a previous stage or a vertical start signal;
a pull-up part outputting a present clock signal of a first clock terminal through an output terminal in response to the signal of the first node;
a first node holding part maintaining the signal of the first node at a ground voltage in response to a clock signal of a stage two stages (m+2) beyond the current stage; and
a gate holding part maintaining a signal of the output terminal at the ground voltage in response to a clock signal of a stage three stages (m+3) beyond the current stage,
wherein the clock signal of the stage three stages (m+3) beyond the current stage is delayed by about ¾ period of the current stage (m) clock signal.
4. The gate drive circuit of claim 3 , further comprising:
a pull-down part outputting the ground voltage through the output terminal in response to one of the next stage or the vertical start signal.
5. The gate drive circuit of claim 3 , wherein a phase of the vertical start signal is synchronized with a phase of the present clock signal, and a pulse width of the vertical start signal is substantially equal to a pulse width of the present clock signal.
6. The gate drive circuit of claim 3 , wherein the first node holding part comprises:
a first maintaining part maintaining the signal of the first node at the ground voltage in response to a signal delayed by about ¾ period of the clock signal of the current stage; and
a second maintaining part maintaining the signal of the first node at the ground voltage in response to the clock signal of the stage two stages (m+2) beyond the current stage.
7. The gate drive circuit of claim 3 , wherein the gate holding part comprises:
a third maintaining part maintaining the signal of the output terminal at the ground voltage in response to a clock signal of a stage one stage (m+1) beyond the current stage; and
a fourth maintaining part maintaining the signal of the output terminal at the ground voltage in response to the clock signal of the stage three stages (m+3) beyond the current stage.