IP Library › Granted Patent US 8,570,780
Granted Patent B2
US 8,570,780 · App. 13/396,934 · Granted Oct 29, 2013

Semiconductor device

Inventors: Shinsuke Godo (Tokyo, JP); Atsunobu Kawamoto (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
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Quick Facts
Patent No.
US 8,570,780
App. No.
13/396,934
Granted
Oct 29, 2013
Kind
B2
Abstract

A semiconductor device includes: a parallel connection structure 1 between a first node and a second node; a first snubber device and a second snubber device having a clamp level that is the same as or higher than the output voltage of a power source section. One terminal of the first snubber device is connected through the first node to one end of the parallel connection structure, the opposite terminal of the first snubber device is connected through a third node to one terminal of the second snubber device, and the opposite terminal of the second snubber device is connected through the second node to the opposite end of the parallel connection structure. Electric power is fed back to the power source section through the second and third nodes.

Claims (42)

1. A semiconductor device, comprising:

a parallel connection structure in which a main switching element and a first diode are connected in parallel between a first node and a second node;

a first snubber device having a clamp level that does not exceed the breakdown voltage of said main switching element; and

a second snubber device having a clamp level that is the same as or higher than the output voltage of a power source section for supplying electric power to a drive circuit for driving said main switching element, wherein

one terminal of said first snubber device is connected through said first node to one end of said parallel connection structure, the opposite terminal of said first snubber device is connected through a third node to one terminal of said second snubber device, and the opposite terminal of said second snubber device is connected through said second node to the opposite end of said parallel connection structure, and

electric power is fed back to said power source section through said second and third nodes.

2. The semiconductor device according to claim 1 , further comprising a second diode provided between said third node and said power source section, the forward direction of the second diode corresponding to a direction from said third node toward said power source section.

3. The semiconductor device according to claim 1 , wherein

said first snubber device includes:

a MOSFET made of a wide band gap material, the MOSFET having a drain terminal at said one terminal of said first snubber device, and a source terminal at said opposite terminal of said first snubber device;

a Zener diode formed between said drain terminal and a gate terminal of said MOSFET; and

a first resistor formed between said source and gate terminals of said MOSFET,

said second snubber device includes an IGBT having a collector terminal corresponding to said one terminal of said second snubber device, and an emitter terminal corresponding to said opposite terminal of said second snubber device, and

the forward direction of said first diode corresponds to a direction from said second node toward said first node.

4. The semiconductor device according to claim 3 , further comprising

a second diode provided between said third node and said power source section, the forward direction of the second diode corresponding to a direction from said third node toward said power source section, wherein

said second diode is a diode parasitic to said IGBT.

5. The semiconductor device according to claim 3 , further comprising

a second diode provided between said third node and said power source section, the forward direction of the second diode corresponding to a direction from said third node toward said power source section, and

a second resistor provided between said second diode and said power source section.

6. The semiconductor device according to claim 5 , further comprising

a CMOS circuit for monitoring the temperatures of said MOSFET and said IGBT, and generating a control signal for controlling said main switching element based on a result of the monitoring, wherein

said CMOS circuit is provided between said second diode and said second node, and

part of said electric power to be fed back to said power source section is supplied to said CMOS circuit.

7. The semiconductor device according to claim 6 , wherein said second resistor is provided between said second diode and said CMOS circuit.

8. The semiconductor device according to claim 6 , wherein said CMOS circuit generates a signal based on a current flowing in a current detecting terminal of said main switching element.

9. The semiconductor device according to claim 6 , further comprising

a temperature detecting element for detecting the temperature of said main switching element, wherein

said CMOS circuit generates a signal based on a result of the detection made by said temperature detecting element.

10. The semiconductor device according to claim 6 , wherein said CMOS circuit monitors a signal at a gate terminal of said IGBT, and generates a control signal for controlling said main switching element based on a result of the monitoring.

11. The semiconductor device according to claim 6 , wherein said CMOS circuit monitors a signal at a current detecting terminal of said IGBT, and generates a control signal for controlling said main switching element based on a result of the monitoring.

12. The semiconductor device according to claim 6 , comprising any one of an NMOS circuit, a bipolar circuit, and a BiCMOS circuit in place of said CMOS circuit.

13. The semiconductor device according to claim 1 , comprising an inverter bridge in place of said parallel connection structure.

14. The semiconductor device according to claim 3 , wherein said MOSFET, said Zener diode, and said first resistor are individual members independent of one another.

15. A semiconductor device, comprising a semiconductor unit and a power source section, wherein

said semiconductor unit includes:

a parallel connection structure in which a main switching element and a first diode are connected in parallel between a first node and a second node;

a first snubber device having a clamp level that does not exceed the breakdown voltage of said main switching element; and

a second snubber device having a clamp level that is the same as or higher than the output voltage of said power source section for supplying electric power to a drive circuit for driving said main switching element,

one terminal of said first snubber device is connected through said first node to one end of said parallel connection structure, the opposite terminal of said first snubber device is connected through a third node to one terminal of said second snubber device, and the opposite terminal of said second snubber device is connected through said second node to the opposite end of said parallel connection structure, and

electric power is fed back to said power source section through said second and third nodes.

16. The semiconductor device according to claim 15 , comprising a bi-directional converter capable of supplying electric power to be fed back from said semiconductor unit to a circuit other than said drive circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2012
From: GODO, SHINSUKE; KAWAMOTO, ATSUNOBU
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 027710/0099 →
Priority Claims (1)
JP 2011-124895 · Jun 3, 2011 · national
Continuity (1)
Related Publication 20120307532A1 · Dec 6, 2012