Energy saving silent mode for hearing implant systems

1. A signal processing arrangement for a cochlear implant system comprising:

a sensing microphone for sensing an acoustic signal to generate a corresponding electrical sound signal;

an information detection circuit for performing spectral analysis on the sound signal to identify the presence of speech information; and

a sound signal processing circuit for generating an implant communications signal for the cochlear implant system based on the sound signal, and having an energy saving operational mode controlled based on a hysteresis threshold wherein the implant communications signal is generated only when the information detection circuit identifies that speech information is present in the sound signal.

2. An arrangement according to claim 1 , wherein a minimum amount of supply voltage is provided to the implant processor when the information detection circuit identifies that no speech information is present in the sound signal.

3. An arrangement according to claim 1 , wherein the hysteresis threshold is software programmable.

4. An arrangement according to claim 1 , wherein the hysteresis threshold is user controllable.

5. An arrangement according to claim 1 , wherein the arrangement includes a minimum operational time requirement for which the sound signal processing circuit is enabled by the information detection circuit.

6. An arrangement according to claim 1 , wherein the information detection circuit includes a voice activation detections (VAD) circuit using a windowed spectral power analysis approach.

7. An arrangement according to claim 1 , further comprising:

a signal delay memory for providing a processing delay to avoid loss of speech information around the time when the information detection circuit initially identifies that speech information is present in the sound signal.

8. An arrangement according to claim 7 , wherein the signal delay memory is in parallel with information detection circuit.

9. An arrangement according to claim 8 , wherein the sound signal processing circuit is in parallel with the information detection circuit and in series with the signal delay memory.

10. An arrangement according to claim 9 , further comprising:

a memory control switch between the sound signal processing circuit and the signal delay memory for controlling whether the implant communications signal passes through or bypasses the signal delay memory.

11. An arrangement according to claim 8 , further comprising:

a direct signal path in parallel with the information detection circuit and the signal delay memory for coupling the sound signal directly to the sound signal processing circuit without delay.

12. An arrangement according to claim 11 , further comprising:

a memory control switch in series with the direct signal path and the signal delay memory for controlling whether the sound signal passes through the direct signal path or the signal delay memory.

13. A cochlear implant system having a signal processing arrangement according to any of claims 1 , 2 , and 3 - 12 .

14. A method for signal processing in a cochlear implant system comprising:

sensing an acoustic signal with a sensing microphone to generate a corresponding electrical sound signal;

performing spectral analysis on the sound signal with an information detection circuit to identify the presence of speech information; and

generating an implant communications signal for the cochlear implant system with a sound signal processing circuit in an energy saving operational mode controlled based on a hysteresis threshold based on the sound signal only when the information detection circuit identifies that speech information is present in the sound signal.

15. A method according to claim 14 , wherein the hysteresis threshold is software programmable.

16. A method according to claim 14 , wherein the hysteresis threshold is user controllable.

17. A method according to claim 14 , wherein generating the implant communications signal satisfies a minimum operational time requirement for which the sound signal processing circuit is enabled by the information detection circuit.

18. A method according to claim 14 , wherein the information detection circuit includes a voice activation detections (VAD) circuit using a windowed spectral power analysis approach.

19. A method according to claim 14 , further comprising:

providing a processing delay with a signal delay memory to avoid loss of speech information around the time when the information detection circuit initially identifies that speech information is present in the sound signal.

20. A method according to claim 19 , wherein the signal delay memory is in parallel with information detection circuit.

21. A method according to claim 20 , wherein the sound signal processing circuit is in parallel with the information detection circuit and in series with the signal delay memory.

22. A method according to claim 21 , further comprising:

controlling with a memory control switch whether the implant communications signal passes through or bypasses the signal delay memory.

23. A method according to claim 21 , further comprising:

coupling the sound signal directly to the sound signal processing circuit without delay.

24. A method according to claim 23 , further comprising:

controlling with a memory control switch whether the sound signal passes through the direct signal path or the signal delay memory.

25. A method according to claim 14 , further comprising:

providing a minimum amount of supply voltage to the implant processor when the information detection circuit identifies that no speech information is present in the sound signal.