JTAG IC with commandable circuit controlling data register control router
The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.
1. An integrated circuit comprising:
a TDI signal lead, a TDO signal lead, a TCK signal lead and a TMS signal lead;
a Tap state machine having an input coupled to the TCK signal lead, an input coupled to the TMS signal lead, instruction register control outputs and data register control outputs;
an instruction register having an input coupled to the TDI signal lead, an output coupled to the TDO signal lead, control inputs coupled to the instruction control outputs of the Tap state machine and enable outputs;
a commandable data register control router including:
(1) a command circuit having an input coupled to the TCK signal lead, an input coupled to the TMS signal lead, and control outputs; and
(2) a routing circuit having first control inputs coupled to the data register control outputs of the Tap state machine, second control inputs coupled to the control outputs of the command circuit, data register control outputs and enable inputs coupled to the enable outputs of the instruction register; and
a data register having an input coupled to the TDI signal lead, an output coupled to the TDO signal lead, and control inputs coupled to the data register control outputs of the routing circuit.
2. The integrated circuit of claim 1 including functional circuitry and the data register is coupled to the functional circuitry.
3. The integrated circuit of claim 1 including functional circuitry and the data register is a debug register coupled to the functional circuitry.
4. The integrated circuit of claim 1 including functional circuitry and the data register is a programming data register coupled to the functional circuitry.
5. The integrated circuit of claim 1 including instrumentation circuitry and the data register is an instrumentation data register coupled to the instrumentation circuitry.
6. The integrated circuit of claim 1 including functional circuitry having interconnects and the data register is a boundary register coupled to the interconnects and the functional circuitry.
7. The integrated circuit of claim 1 including functional circuitry and the data register is a boundary register coupled to the functional circuitry.
8. The integrated circuit of claim 1 including core circuitry having core interconnects and the data register is a core wrapper boundary register coupled to the core interconnects circuitry.
9. The integrated circuit of claim 1 including core system logic and the data register is a core wrapper boundary register coupled to the core system logic.
10. The integrated circuit of claim 1 including functional circuitry having interconnects and another integrated circuit having interconnects and the data register is a boundary register coupled to the interconnects of the functional circuitry and the other integrated circuit.
11. The integrated circuit of claim 1 including first core circuitry and second core circuitry separate from the integrated circuit and the data register is a core wrapper boundary register coupled between the two cores.
12. The integrated circuit of claim 1 including first core circuitry and second core circuitry separate from the integrated circuit, the first core circuitry and the second core circuitry being coupled together and the data register is a boundary register coupled between the first core circuitry and the second core circuitry.