Gate structures

1. A semiconductor device, comprising:

a semiconductor substrate;

first and second projections extending upwardly from the substrate, the projections having respective first and second channel regions therein;

a first gate structure engaging the first projection adjacent the first channel region, the first gate structure including:

a first dielectric material over the first channel region;

a first opening over the first dielectric material and the first channel region; and

a pure first metal with an n-type work function value and a low resistivity conformally deposited in the first opening;

a second gate structure engaging the second projection adjacent the second channel region, the second gate structure including:

a second dielectric material over the second channel region;

a second opening over the second dielectric material and the second channel region; and

a pure second metal with a p-type work function value and a low resistivity conformally deposited in the second opening.

2. A semiconductor device according to claim 1 ,

wherein the pure first metal completely fills the first opening; and

wherein the pure second metal completely fills the second opening.

3. A semiconductor device according to claim 1 , wherein the pure first metal is one of aluminum (Al) and tantalum (Ta).

4. A semiconductor device according to claim 1 , wherein the pure second metal is one of cobalt (Co), nickel (Ni), and platinum (Pt).

5. A semiconductor device according to claim 1 ,

wherein the first and second channel regions are long channel regions;

wherein the pure first metal fills a portion of the first opening;

wherein the pure second metal fills a portion of the second opening; and

including a fill metal disposed in the in remaining portions of the first and second openings.

6. A semiconductor device according to claim 1 , wherein the first opening and the second opening each have a high aspect ratio.

7. A semiconductor device according to claim 1 ,

wherein the first projection and first gate structure are portions of a p-type metal oxide semiconductor (PMOS) device; and

wherein the second projection and second gate structure are portions of an n-type metal oxide semiconductor (NMOS) device.

8. A semiconductor device, comprising:

a semiconductor substrate;

a first short-channel fin-like field effect transistor (FinFET) disposed over the semiconductor substrate and including a first gate structure adjacent a first channel region, the first gate structure including a high-k dielectric layer and a first pure metal gate electrode composed of a first metal; and

a second short-channel FinFET disposed adjacent the first FinFET and over the semiconductor substrate, the second short-channel FinFET including a second gate structure adjacent a second channel region, and the second gate structure including the high-k dielectric layer and a second pure metal gate electrode composed of a second metal different than the first metal.

9. A semiconductor device according to claim 8 , wherein the first metal has an n-type work function value and the second metal has a p-type work function value.

10. A semiconductor device according to claim 9 , wherein the first metal is one of aluminum (Al) and tantalum (Ta).

11. A semiconductor device according to claim 9 , wherein the second metal is one of cobalt (Co), nickel (Ni), and platinum (Pt).

12. A semiconductor device according to claim 8 , wherein the first and second pure metal gate electrodes are disposed within respective openings that each have a high-aspect ratio.

13. A semiconductor device according to claim 8 , wherein the first gate structure includes a barrier layer disposed between the high-k dielectric layer and the first pure metal gate electrode.

14. A semiconductor device according to claim 13 , wherein the barrier layer includes one of titanium nitride (TiN), tantalum nitride (TaN), and a metal carbide.