IP Library Granted Patent US 8,577,949
Granted Patent B2
US 8,577,949 · App. 12/498,800 · Granted Nov 5, 2013

System for conjugate gradient linear iterative solvers

Inventors: Matthew P. DeLaquil (Rockwall, TX); Deepak Prasanna (Rockwall, TX); Antone L. Kusmanoff (Greenville, TX)
Assignee: L-3 Communications Integrated Systems, L.P.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,577,949
App. No.
12/498,800
Granted
Nov 5, 2013
Kind
B2
Abstract

A system for a conjugate gradient iterative linear solver that calculates the solution to a matrix equation comprises a plurality of gamma processing elements, a plurality of direction vector processing elements, a plurality of x-vector processing elements, an alpha processing element, and a beta processing element. The gamma processing elements may receive an A-matrix and a direction vector, and may calculate a q-vector and a gamma scalar. The direction vector processing elements may receive a beta scalar and a residual vector, and may calculate the direction vector. The x-vector processing elements may receive an alpha scalar, the direction vector, and the q-vector, and may calculate an x-vector and the residual vector. The alpha processing element may receive the gamma scalar and a delta scalar, and may calculate the alpha scalar. The beta processing element may receive the residual vector, and may calculate the delta scalar and the beta scalar.

Claims (48)

1. A system for a conjugate gradient iterative linear solver that calculates the solution to a matrix equation, the system comprising:

a field programmable gate array (FPGA), including a plurality of configurable logic elements and a plurality of configurable storage elements;

a plurality of gamma processing elements formed from configurable logic elements and configurable storage elements, and configured to receive an A-matrix and a direction vector, and to calculate a q-vector and a gamma scalar;

a plurality of direction vector processing elements formed from configurable logic elements and configurable storage elements, and configured to receive a beta scalar and a residual vector, and to calculate the direction vector;

a plurality of x-vector processing elements formed from configurable logic elements and configurable storage elements, and configured to receive an alpha scalar, the direction vector, and the q-vector, and to calculate an x-vector and the residual vector;

an alpha processing element formed from configurable logic elements and configurable storage elements, and configured to receive the gamma scalar and a delta scalar, and to calculate the alpha scalar; and

a beta processing element formed from configurable logic elements and configurable storage elements, and configured to receive the residual vector, and to calculate the delta scalar and the beta scalar.

2. The system of claim 1 , wherein the q-vector is a product of the A-matrix and the direction vector.

3. The system of claim 1 , wherein the gamma scalar is a dot product of the q-vector and the direction vector.

4. The system of claim 1 , wherein the direction vector is a sum of the residual vector and a product of the beta scalar and a previous iteration of the direction vector.

5. The system of claim 1 , wherein the residual vector is a difference of a previous iteration of the residual vector and a product of the alpha scalar and the q-vector.

6. The system of claim 1 , wherein the x-vector is a sum of a previous iteration of the x-vector and a product of the alpha scalar and the direction vector.

7. The system of claim 1 , wherein the alpha scalar is a quotient of the delta scalar and the gamma scalar.

8. The system of claim 1 , wherein the delta scalar is a dot product of the residual vector with itself.

9. The system of claim 1 , wherein the beta scalar is a quotient of a current iteration of the delta scalar and a previous iteration of the delta scalar.

10. The system of claim 1 , wherein each gamma processing element receives a portion of the A-matrix and a portion of the direction vector, and calculates a portion of the q-vector and a portion of the gamma scalar.

11. The system of claim 1 , wherein each direction vector processing element receives the beta scalar and a portion of the residual vector, and calculates a portion of the direction vector.

12. The system of claim 1 , wherein each x-vector processing element receives the alpha scalar, a portion of the q-vector, and a portion of the direction vector, and calculates a portion of the x-vector and a portion of the residual vector.

13. The system of claim 1 , wherein the residual vector initially is a difference between a b-vector and a product of the A-matrix and the x-vector.

14. A system for a conjugate gradient iterative linear solver that calculates the solution to a matrix equation, the system comprising:

a plurality of field programmable gate arrays (FPGAs), including a plurality of configurable logic elements and a plurality of configurable storage elements;

a plurality of gamma processing elements formed from configurable logic elements and configurable storage elements, and configured to receive an A-matrix and a direction vector, and to calculate a q-vector and a gamma scalar;

a plurality of direction vector processing elements formed from configurable logic elements and configurable storage elements, and configured to receive a beta scalar and a residual vector, and to calculate the direction vector;

a plurality of x-vector processing elements formed from configurable logic elements and configurable storage elements, and configured to receive an alpha scalar, the direction vector, and the q-vector, and to calculate an x-vector and the residual vector;

an alpha processing element formed from configurable logic elements and configurable storage elements, and configured to receive the gamma scalar and a delta scalar, and to calculate the alpha scalar;

a beta processing element formed from configurable logic elements and configurable storage elements, and configured to receive the residual vector, and to calculate the delta scalar and the beta scalar; and

a plurality of inter FPGA links, each inter FPGA link included within one FPGA and configured to allow communication from one FPGA to another FPGA.

15. The system of claim 14 , wherein the q-vector is a product of the A-matrix and the direction vector.

16. The system of claim 14 , wherein the gamma scalar is a dot product of the q-vector and the direction vector.

17. The system of claim 14 , wherein the direction vector is a sum of the residual vector and a product of the beta scalar and a previous iteration of the direction vector.

18. The system of claim 14 , wherein the residual vector is a difference of a previous iteration of the residual vector and a product of the alpha scalar and the q-vector.

19. The system of claim 14 , wherein the x-vector is a sum of a previous iteration of the x-vector and a product of the alpha scalar and the direction vector.

20. The system of claim 14 , wherein the alpha scalar is a quotient of the delta scalar and the gamma scalar.

21. The system of claim 14 , wherein the delta scalar is a dot product of the residual vector with itself.

22. The system of claim 14 , wherein the beta scalar is a quotient of a current iteration of the delta scalar and a previous iteration of the delta scalar.

23. The system of claim 14 , wherein each gamma processing element receives a portion of the A-matrix and a portion of the direction vector, and calculates a portion of the q-vector and a portion of the gamma scalar.

24. The system of claim 14 , wherein each direction vector processing element receives the beta scalar and a portion of the residual vector, and calculates a portion of the direction vector.

25. The system of claim 14 , wherein each x-vector processing element receives the alpha scalar, a portion of the q-vector, and a portion of the direction vector, and calculates a portion of the x-vector and a portion of the residual vector.

26. The system of claim 14 , wherein the residual vector initially is a difference between a b-vector and a product of the A-matrix and the x-vector.

27. A system for a conjugate gradient iterative linear solver that calculates the solution to a matrix equation, the system comprising:

a plurality of field programmable gate arrays (FPGAs), including a plurality of configurable logic elements and a plurality of configurable storage elements;

a plurality of gamma processing elements formed from configurable logic elements and configurable storage elements, and configured to receive an A-matrix and a direction vector, and to calculate a q-vector and a gamma scalar, wherein the q-vector is a product of the A-matrix and the direction vector, and the gamma scalar is a dot product of the q-vector and the direction vector;

a plurality of direction vector processing elements formed from configurable logic elements and configurable storage elements, and configured to receive a beta scalar and a residual vector, and to calculate the direction vector, wherein the direction vector is a sum of the residual vector and a product of the beta scalar and a previous iteration of the direction vector;

a plurality of x-vector processing elements formed from configurable logic elements and configurable storage elements, and configured to receive an alpha scalar, the direction vector, and the q-vector, and to calculate an x-vector and the residual vector, wherein the x-vector is a sum of a previous iteration of the x-vector and a product of the alpha scalar and the direction vector, and the residual vector is a difference of a previous iteration of the residual vector and a product of the alpha scalar and the q-vector;

an alpha processing element formed from configurable logic elements and configurable storage elements, and configured to receive the gamma scalar and a delta scalar, and to calculate the alpha scalar, wherein the alpha scalar is a quotient of the delta scalar and the gamma scalar;

a beta processing element formed from configurable logic elements and configurable storage elements, and configured to receive the residual vector, and to calculate the delta scalar and the beta scalar, wherein the delta scalar is a dot product of the residual vector with itself, and the beta scalar is a quotient of a current iteration of the delta scalar and a previous iteration of the delta scalar; and

a plurality of inter FPGA links, each inter FPGA link included within one FPGA and configured to allow communication from one FPGA to another FPGA.

28. The system of claim 27 , wherein the residual vector initially is a difference between a b-vector and a product of the A-matrix and the x-vector.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME FROM L3 COMMUNICATIONS INTEGRATED SYSTEMS, L.P. TO L-3 COMMUNICATIONS INTEGRATED SYSTEMS, L.P. PREVIOUSLY RECORDED ON REEL 023106 FRAME 0195. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 19, 2012
From: DELAQUIL, MATTHEW P.; KUSMANOFF, ANTONE L.
To: L-3 COMMUNICATIONS INTEGRATED SYSTEMS, L.P.
Reel/Frame 029499/0346 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2009
From: DELAQUIL, MATTHEW P.; KUSMANOFF, ANTONE L.; PRASANNA, DEEPAK
To: L3 COMMUNICATIONS INTEGRATED SYSTEMS, L.P.
Reel/Frame 023106/0195 →
Continuity (1)
Related Publication 20110010409A1 · Jan 13, 2011