Infrastructure support for accelerated processing device memory paging without operating system integration
In a CPU, the CPU having multiple CPU cores, each core having a first machine specific register, a second machine specific register, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.
1. A method of operating a combined CPU/APD architecture system, comprising:
responsive to a determination that a control register of a CPU core has been updated, issuing a write notification to a location controlled by an IOMMUv2;
wherein the location controlled by the IOMMUv2 is configured to receive writes that affect IOMMUv2 page table invalidations.
2. The method of claim 1 , further comprising:
receiving in a first machine specific register of a CPU core, a physical page table/page directory base address;
receiving in a second machine specific register of the CPU core, a physical address pointing to the location controlled by the IOMMUv2; and
determining that the control register of the CPU core has been updated.
3. The method of claim 2 , wherein the first machine specific register receives the physical page table/page directory base address which the IOMMUv2 is using at the time for its process context.
4. The method of claim 2 , wherein the control register is one in which a physical page table/page directory base address is disposed.
5. The method of claim 3 , wherein the current physical page table/page directory base address is received by the first machine specific register as a result of executing an IOMMUv2 driver.
6. The method of claim 2 , wherein the CPU core is an x86 core.
7. The method of claim 2 , wherein the first machine specific register receives the physical page table/page directory base address which the IOMMUv2 is using at the time for its process context; wherein the control register is one in which a physical page table/page directory base address is disposed; and further comprising:
determining whether the physical page table/page directory base address in the first machine specific register and the physical page table/page directory base address in the control register are the same.
8. The method of claim 7 , wherein the control register is an x86 CR3 register.
9. The method of claim 7 , further comprising:
receiving at the IOMMUv2 an indication that no CPU core is carrying the same page table base address in the control register as the IOMMUv2; and
issuing, responsive thereto, a global page table invalidation.
10. The method of claim 7 , wherein the write notification comprises a first message if the physical page table/page directory base address in the first machine specific register and the physical page table/page directory base address in the control register are the same.
11. The method of claim 7 , wherein the write notification comprises a second message if the physical page table/page directory base address in the first machine specific register and the physical page table/page directory base address in the control register are not the same;
wherein the first message and the second message are different from each other.
12. The method of claim 2 , wherein a memory location corresponding to the physical address is located in a system memory.
13. The method of claim 2 , wherein a memory location corresponding to the physical address is located in the IOMMUv2.
14. The method of claim 2 , wherein the IOMMUv2 is communicatively coupled to a graphics processing device.
15. The method of claim 9 , wherein the IOMMUv2 is communicatively coupled to a graphics processing device; and further comprising:
tracking any invalidation for APD shader virtual memory accesses.
16. The method of claim 10 , further comprising determining whether one or more bits of a second CPU control register have been modified.
17. A method of operating a combined CPU/APD architecture system, the CPU having a plurality of x86 cores, comprising:
determining, in a CPU core, that a TLB invalidation has occurred and that this invalidation is related to a page table/page directory the base address of which is stored in a first machine specific register of the CPU core; and
responsive to the determination that the TLB invalidation has occurred, executing microcode that causes a write notification to be issued to the location specified by a physical address in a second machine specific register.
18. The method of claim 17 , further comprising:
receiving in the first machine specific register of the CPU core, a physical page table/page directory base address;
receiving in the second machine specific register of the CPU core, the physical address pointing to a location controlled by an IOMMUv2.
19. The method of claim 17 , wherein executing the microcode is performed in the CPU core.
20. The method of claim 18 , wherein the write notification comprises:
a first message; and
a second message if the physical page table/page directory base address in the first machine specific register and another physical page table/page directory base address in a CPU core control register in which physical page table/page directory base address information is disposed are not the same;
wherein the first message and the second message are different from each other.