IP Library › Granted Patent US 8,580,648
Granted Patent B2
US 8,580,648 · App. 13/035,342 · Granted Nov 12, 2013

Capacitor having an electrode structure, method of manufacturing a capacitor having an electrode structure and semiconductor device having an electrode structure

Inventors: Suk-Hun Choi (Suwon-si, KR); Kyung-Hyun Kim (Seoul, KR); Chang-Sup Mun (Suwon-si, KR); Sung-Jun Kim (Hwaseong-si, KR); Jin-I Lee (Yongin-si, KR)
Assignee: Samsung Electronics Co., Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,580,648
App. No.
13/035,342
Granted
Nov 12, 2013
Kind
B2
Abstract

A capacitor includes an object or a substrate including an insulation layer having an opening, an electrode structure having conductive patterns, a dielectric layer and an upper electrode. The electrode structure may have a first conductive pattern including metal and a second conductive pattern including metal oxide generated from the first conductive pattern. The first conductive pattern may fill the opening and may protrude over the insulation layer. The second conductive pattern may extend from the first conductive pattern. The electrode structure may additionally include a third conductive pattern disposed on the second conductive pattern. The capacitor including the electrode structure may ensure improved structural stability and electrical characteristics.

Claims (12)

1. A method of manufacturing a capacitor, comprising:

forming an insulation layer on a substrate;

forming a first conductive pattern including metal buried in the insulation layer;

forming a second conductive pattern including metal oxide generated from the first conductive pattern;

forming a third conductive pattern on the second conductive pattern;

forming a dielectric layer on the second and the third conductive patterns; and

forming an upper electrode on the dielectric layer;

forming a first sacrificial layer on the insulation layer before forming the second conductive pattern;

forming a second sacrificial layer on the first sacrificial layer to cover the second conductive pattern;

forming an opening by etching the second sacrificial layer, the opening exposing the second conductive pattern; and

forming a third conductive pattern on the second conductive pattern and a sidewall of the opening.

2. The method of claim 1 , wherein forming the third conductive pattern further comprises forming a supporting member between adjacent elements of the third conductive patterns.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2011
From: CHOI, SUK-HUN; KIM, KYUNG-HYUN; MUN, CHANG-SUP; KIM, SUNG-JUN; LEE, JIN-I
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 026720/0482 →
Priority Claims (1)
KR 10-2010-0017134 · Feb 25, 2010 · national
Continuity (1)
Related Publication 20110204427A1 · Aug 25, 2011