IP Library Granted Patent US 8,580,652
Granted Patent B2
US 8,580,652 · App. 12/875,628 · Granted Nov 12, 2013

Semiconductor device and manufacturing method thereof

Inventors: Atsuko Kawasaki (Yokohama, JP); Kenichiro Hagiwara (Yokohama, JP); Ikuko Inoue (Yokohama, JP); Kazutaka Akiyama (Matsudo, JP); Itsuko Sakai (Yokohama, JP); Mie Matsuo (Kamakura, JP); Masahiro Sekiguchi (Yokohama, JP); Yoshiteru Koseki (Kitakami, JP); Hiroki Neko (Kitakami, JP); Koushi Tozuka (Hanamaki, JP); Kazuhiko Nakadate (Yokohama, JP); Takuto Inoue (Kitakami, JP)
Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,580,652
App. No.
12/875,628
Granted
Nov 12, 2013
Kind
B2
Abstract

According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having first and second main surfaces, and a through hole passing through between the first and second main surfaces, a pad on the first main surface, a through electrode in the through hole, and a connection structure including a connection portion to directly connect the pad and the through electrode, and another connection portion to indirectly connect the pad and the through electrode. The method includes forming an isolation region in the first main surface, the isolation region being in a region where the through electrode is to be formed and being in a region other than the region where the through hole is to be formed, forming the pad, and forming the through hole by processing the substrate to expose a part of the pad.

Claims (21)

1. A method for manufacturing a semiconductor device, comprising:

forming an isolation region in a main surface of a semiconductor substrate, the isolation region comprising an isolation insulating film filling a trench formed in the main surface, and the isolation region being in a region where a through hole of the semiconductor substrate is to be formed and being in a region other than the region where the through hole is to be formed wherein the through hole passes through the main surface;

forming an interlayer insulating film on the main surface;

forming an electrode pad on the interlayer insulating film;

forming the through hole by processing the semiconductor substrate and the interlayer insulating film such that a part of the electrode pad is exposed in the through hole and the interlayer insulating film is thinned in the through hole; and

forming a through electrode in the through hole, wherein the through electrode contacts the exposed part of the electrode pad and the thinned interlayer insulating film.

2. The method according to claim 1 , wherein the forming the isolation region comprises forming the trench in the main surface, forming an insulating film to be the isolation insulating film on the main surface, and polishing the insulating film by CMP process.

3. The method according to claim 1 , wherein the region other than the region where the through hole is to be formed includes a region where a peripheral circuit is to be formed.

4. The method according to claim 1 , further comprises filling the through hole with a protective film after forming the through electrode.

5. The method according to claim 4 , wherein the protective film comprises a solder resist.

6. The method according to claim 1 , further comprises forming a dummy electrode in the region where the through hole is to be formed, and wherein the dummy electrode is formed without overlapping with the isolation insulating film.

7. A method for manufacturing a semiconductor device, comprising:

forming an isolation region in a main surface of a semiconductor substrate, the isolation region comprising an isolation insulating film filling a trench formed in the main surface, and the isolation region being in a region other than a region where a through hole of the semiconductor substrate is to be formed wherein the through hole passes through the main surface;

forming a dummy electrode selectively in the region where the through hole is to be formed;

forming an interlayer insulating film on the main surface;

forming an electrode pad on the interlayer insulating film;

forming the through hole by processing the semiconductor substrate, and the interlayer insulating film such that a part of the electrode pad is exposed in the through hole and the interlayer insulating film is thinned in the through hole; and

forming a through electrode in the through hole, wherein the through electrode contacts the exposed part of the electrode pad and the thinned interlayer insulating film.

8. The method according to claim 7 , wherein the forming the isolation region comprises forming the trench in the main surface, forming an insulating film to be the isolation insulating film on the main surface, and polishing the insulating film by CMP process.

9. The method according to claim 7 , wherein the region other than the region where the through hole is to be formed includes a region where a peripheral circuit is to be formed.

10. The method according to claim 7 , further comprises filling the through hole with a protective film after forming the through electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2010
From: KAWASAKI, ATSUKO; HAGIWARA, KENICHIRO; INOUE, IKUKO; AKIYAMA, KAZUTAKA; SAKAI, ITSUKO; MATSUO, MIE; SEKIGUCHI, MASAHIRO; KOSEKI, YOSHITERU; NEKO, HIROKI; TOZUKA, KOUSHI; NAKADATE, KAZUHIKO; INOUE, TAKUTO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 024939/0894 →
Priority Claims (1)
JP 2009-219736 · Sep 24, 2009 · national
Continuity (1)
Related Publication 20110068476A1 · Mar 24, 2011