Method for fabricating semiconductor device

1. A method for forming a semiconductor device comprising:

forming an interlayer insulating film;

forming a bit line contact trench in the interlayer insulating film;

forming a spacer at sidewalls of the bit line contact trench;

forming a first bit line contact conductive layer over the bit line contact trench;

etching the first bit line contact conductive layer to form a first bit line contact buried between the spacer;

removing an exposed portion of the spacer after forming the first bit line contact;

forming a second bit line contact over the first bit line contact that is coupled to the first bit line contact and has a width larger than the first bit line contact; and

forming a bit line over the second bit line contact.

2. The method according to claim 1 , further comprising:

performing a planarization etching process on the first bit line contact conductive layer so as to expose the interlayer insulating film.

3. The method according to claim 1 , wherein the etching of the first bit line contact conductive layer is performed by dry-etching or wet-etching.

4. The method according to claim 1 , wherein the etching of the first bit line contact conductive layer includes etching the first bit line contact conductive layer by a depth that is about half a depth of the bit line contact trench.

5. The method according to claim 1 ,

wherein removing the exposed portion of the spacer is performed by a wet etching or an isotropic dry etching process.

6. The method according to claim 1 , the method further comprising:

performing wet cleaning at an upper part of the first bit line contact.

7. The method according to claim 1 , wherein the forming of the second bit line contact includes:

forming a second bit line contact conductive layer over the first bit line contact; and

performing a planarization etching process or an etch-back process on the second bit line contact conductive layer to expose the interlayer insulating film.

8. The method according to claim 1 , wherein the forming of the bit line includes:

forming a bit line electrode over the second bit line contact;

forming a hard mask layer over the bit line electrode; and

etching the hard mask layer and the bit line electrode.

9. The method according to claim 1 , the method further comprising forming a barrier metal layer between the bit line and the second bit line contact.

10. The method according to claim 1 , the method further comprising forming a spacer at sidewalls of the bit line.

11. The method according to claim 1 , the method further comprising forming a buried gate buried in the semiconductor substrate.

12. The method according to claim 1 , wherein the forming of the first bit line includes:

forming an interlayer insulating film over the semiconductor substrate;

forming a bit line contact trench in the interlayer insulation film;

forming a spacer over sidewalls of the bit line contact trench;

forming a first bit line contact conductive layer filling in the bit line contact trench; and

etching the first bit line contact conductive layer in such a manner that the bit line contact trench is buried between the spacers.

13. The method of claim 1 , wherein the portion of the spacer removed is exposed by the etching of the first bit line contact conductive layer to form the first bit line contact.

14. A method for forming a semiconductor device comprising:

forming an interlayer insulating film over a substrate;

forming a trench in the interlayer insulating film, the trench exposing an active region defined in the substrate;

forming a spacer at a sidewall of the trench, the spacer including dielectric material and defining an opening within the trench;

providing a conductive layer over the trench, the conductive layer being provided within the opening defined by the spacer;

etching the conductive layer to form a first bit line contact, the first bit line contact exposing an upper portion of the spacer that is formed at the sidewall of the trench;

etching the upper portion of the spacer;

forming a second bit line contact within the trench and over the first bit line contact and the etched spacer, the second bit line contact having a width larger than the first bit line contact; and

forming a bit line over the second bit line contact.

15. The method of claim 14 , wherein the active region is exposed by the opening defined by the spacer, and

wherein the conductive layer is provided over the active region and makes an electrical contact with the active region.

16. The method of claim 15 , wherein the substrate includes silicon material, and the trench extends into the silicon material of the substrate, and

wherein the spacer extends to a bottom of the trench and extends into the silicon material.