Recovery and synchronization for spread spectrum modulated clock
Embodiments allow for the use of the SS modulation technique (and thus for significant reduction of EMI due to clock transmission) in scenarios involving tight synchronization requirements between two devices. In particular, embodiments can be used in high-speed communication networks (e.g., high-speed Ethernet) where a clock signal embedded in the data stream at the transmitter and recovered from the data stream at the receiver is the only source for synchronization between the transmitter and the receiver (i.e., no other synchronization channel available). Embodiments are also especially useful in communication systems utilizing echo cancellers.
1. A system, comprising:
a clock and data recovery (CDR) circuit configured to receive a data stream having embedded therein a spread spectrum (SS) modulated clock signal and to generate a recovered clock signal from the data stream;
a phase tracking circuit, coupled to the CDR circuit, configured to determine a phase offset between the recovered clock signal and a local clock signal;
a controller configured to read the determined phase offset and to generate a control signal based on the determined phase offset; and
an oscillator configured to adjust the local clock signal based on the control signal, thereby reducing the phase offset between the recovered clock signal and the local clock signal.
2. The system of claim 1 , wherein the SS modulated clock signal is frequency modulated.
3. The system of claim 1 , wherein the controller is further configured to implement a proportional-integral-derivative (PID) controller algorithm.
4. The system of claim 3 , wherein the controller is further configured to set the determined phase offset as an error signal in the PID controller algorithm.
5. The system of claim 4 , wherein the control signal corresponds to an output signal of the PID controller algorithm.
6. The system of claim 1 , wherein the control signal provides a setpoint value for the oscillator.
7. The system of claim 1 , further comprising:
a phase offset register, wherein the phase tracking circuit is further configured to store the determined phase offset in the phase offset register.
8. The system of claim 7 , wherein the controller is farther configured to sample periodically the phase offset register to read the determined phase offset.
9. The system of claim 8 , wherein the controller is further configured to sample the phase offset register according to an expected rate of change of the determined phase offset.
10. The system of claim 1 , further comprising:
a digital phase locked loop (PLL) configured to generate a predicted phase value of the recovered clock signal; and
a control circuit configured to generate a predicted phase offset based on the predicted phase value and the local clock signal and to control the oscillator based on the predicted phase offset.
11. The system of claim 10 , wherein the digital PLL is further configured to generate the predicted phase value of the recovered clock signal based on known modulation characteristics of the SS modulated clock signal.
12. The system of claim 10 , wherein the controller is further configured to correct periodically the predicted phase offset upon reading the determined phase offset.
13. The system of claim 10 , further comprising:
a low pass filter configured to filter a phase signal of the recovered clock signal and to provide a filtered phase signal of the recovered clock signal to the digital PLL.
14. The system of claim 1 , wherein the oscillator is one of a numerically controlled oscillator (NCO) and a voltage controlled oscillator (VCO).
15. The system of claim 1 , further comprising:
an echo canceller configured to use the recovered clock signal and the local clock signal to reduce an echo due to a stream transmitted by the system in the received data stream.
16. A method, comprising:
sending a status signal regarding operability with spread spectrum (SS) clock modulation;
receiving a data stream having embedded therein a SS modulated clock signal responsive to the status signal;
generating a recovered clock signal from the data stream;
calculating a phase offset between the recovered clock signal and a local clock signal; and
adjusting the local clock signal according to the calculated phase offset to reduce a phase shift between the recovered clock signal and the local clock signal.
17. The method of claim 16 , wherein said adjusting step further comprises:
generating a control signal based on the calculated phase offset; and
adjusting the local clock signal using the control signal.
18. The method of claim 16 , further comprising:
receiving a control signal regarding operability with SS clock modulation;
sending the status signal in response to said control signal.
19. The method of claim 16 , further comprising prior to said receiving step:
receiving information regarding modulation characteristics of said SS modulated clock signal.
20. The method of claim 19 , further comprising:
generating a predict phase offset based on said received information regarding modulation characteristics; and
adjusting the local clock signal based on the predicted phase offset in between periodical adjustments of the local clock signal based on the calculated phase offset.
21. The method of claim 19 , further comprising:
generating a predicted phase offset based on scrambler information regarding modulation characteristics; and
adjusting the local clock signal based on the predicted phase offset.