IP Library › Granted Patent US 8,592,259
Granted Patent B2
US 8,592,259 · App. 13/306,787 · Granted Nov 26, 2013

Method of fabricating a wafer level semiconductor package having a pre-formed dielectric layer

Inventors: Kevin (Kunzhong) Hu (Irvine, CA); Chonghua Zhong (Irvine, CA); Edward Law (Ladera Ranch, CA)
Assignee: Broadcom Corporation
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Quick Facts
Patent No.
US 8,592,259
App. No.
13/306,787
Granted
Nov 26, 2013
Kind
B2
Abstract

There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Claims (28)

1. A method for producing a wafer level semiconductor package, said method comprising:

forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, said first dielectric layer being a pre-formed dielectric layer between said wafer and said second dielectric layer;

forming a window for receiving an electrical contact body in said second dielectric layer, said window exposing said post-Fab RDL.

2. The method of claim 1 , wherein said pre-formed dielectric layer comprises a build-up material.

3. The method of claim 1 , wherein said pre-formed dielectric layer comprises an Ajinomoto™ Build-up Film (ABF).

4. The method of claim 1 , wherein said pre-formed dielectric layer is affixed using a lamination process.

5. The method of claim 1 , wherein said window is formed using a direct laser ablation process.

6. The method of claim 1 , further comprising forming an under-bump metallization (UBM) in said window prior to receiving said electrical contact body.

7. The method of claim 1 , further comprising receiving said electrical contact body in said window so as to electrically couple said electrical contact body to said post-Fab RDL.

8. The method of claim 1 , wherein said electrical contact body is a solder ball.

9. A method for producing a wafer level semiconductor package, said method comprising:

forming a post-fabrication redistribution layer (post-Fab RDL) between a first pre-formed dielectric layer and a second pre-formed dielectric layer affixed over a surface of wafer;

forming a window for receiving an electrical contact body in said second pre-formed dielectric layer, said window exposing said post-Fab RDL.

10. The method of claim 9 , wherein at least one of said first pre-formed dielectric layer and said second pre-formed dielectric layer comprises an Ajinomoto™ Build-up Film (ABF).

11. The method of claim 9 , wherein said first pre-formed dielectric layer and said second pre-formed dielectric layer are affixed using a lamination process.

12. The method of claim 9 , wherein said window is formed using a direct laser ablation process.

13. The method of claim 9 , further comprising forming an under-bump metallization (UBM) in said window prior to receiving said electrical contact body.

14. The method of claim 9 , wherein said electrical contact body is a solder ball.

15. A method for producing a wafer level semiconductor package, said method comprising:

forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, said first dielectric layer being a pre-formed dielectric layer between said wafer and said second dielectric layer;

forming an under-bump metallization (UBM);

forming a window for receiving an electrical contact body in said second dielectric layer, said window exposing said post-Fab RDL;

electrically coupling said electrical contact body to said post-Fab RDL.

16. The method of claim 15 , wherein said pre-formed dielectric layer comprises a build-up material.

17. The method of claim 15 , wherein said pre-formed dielectric layer comprises an Ajinomoto™ Build-up Film (ABF).

18. The method of claim 15 , wherein said pre-formed dielectric layer is affixed using a lamination process.

19. The method of claim 15 , wherein said window is formed using a direct laser ablation process.

20. The method of claim 15 , wherein said electrical contact body is a solder ball.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2011
From: HU, KEVIN (KUNZHONG); ZHONG, CHONGHUA; LAW, EDWARD
To: BROADCOM CORPORATION
Reel/Frame 027294/0225 →
Continuity (1)
Related Publication 20130134596A1 · May 30, 2013