Method of fabricating openings
A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.
1. A method of fabricating openings comprising:
providing a semiconductor substrate having a salicide region thereon, wherein an etch stop layer and at least a dielectric layer disposed on the semiconductor substrate from bottom to top, and the etch stop layer directly contacts the dielectric layer;
patterning the dielectric layer and the etching stop layer to form a plurality of openings in the dielectric layer and the etching stop layer, the openings exposing the salicide region;
forming a dielectric thin film covering the dielectric layer, sidewalls of the openings, and the salicide region; and
removing the dielectric thin film disposed on the dielectric layer and the salicide region.
2. The method of claim 1 , wherein the openings comprise contact holes.
3. The method of claim 1 , wherein the dielectric thin film comprises a silicon oxide thin film, a silicon nitride thin film, or a silicon oxynitride thin film.
4. The method of claim 1 , wherein the dielectric thin film comprises a tantalum oxide thin film, a titanium oxide thin film, a zirconium oxide thin film, a hafnium oxide thin film, hafnium silicon oxide thin film, or hafnium silicon oxynitride.
5. The method of claim 1 , wherein the dielectric thin film comprises a high k material having a dielectric constant greater than 3.9.
6. The method of claim 1 , wherein the openings have a dimension of between 50 and 100 nm, and the dielectric thin film has a thickness of between 0.5 to 10 nm.
7. The method of claim 1 , further comprising:
performing a clean process prior to forming the dielectric thin film.
8. The method of claim 1 , wherein patterning the dielectric layer and the etching stop layer is carried out by a mask layer together with an etching process, and the mask layer comprises a photoresist layer, a metal layer, or a dielectric layer.
9. The method of claim 1 , further comprising:
performing a surface treatment subsequent to removing the dielectric thin film disposed on the dielectric layer and the salicide region.
10. The method of claim 9 , wherein the surface treatment comprises an implantation process or a clean process.
11. The method of claim 1 , wherein the dielectric layer is an inter-layer dielectric (ILD) layer.
12. The method of claim 11 , wherein the dielectric layer comprises at least one of tetraethylorthosilicate (TEOS) oxide, un-doped silicon glass and doped silicon oxide.
13. The method of claim 1 , wherein the dielectric thin film remains on the sidewalls of the openings after removing the dielectric thin film disposed on the dielectric layer and the salicide region.