Self-aligned metal oxide TFT with reduced number of masks
A method of fabricating MOTFTs on transparent substrates by positioning opaque gate metal on the substrate front surface and depositing gate dielectric material overlying the gate metal and a surrounding area and metal oxide semiconductor material on the dielectric material. Depositing selectively removable etch stop material on the semiconductor material and photoresist on the etch stop material to define an isolation area in the semiconductor material. Removing uncovered portions of the etch stop. Exposing the photoresist from the substrate rear surface using the gate metal as a mask and removing exposed portions leaving the etch stop material overlying the gate metal covered. Etching the semiconductor material to isolate the TFT. Selectively etching the etch stop layer to leave a portion overlying the gate metal defining a channel area. Depositing and patterning conductive material to form source and drain areas on opposed sides of the channel area.
1. A metal oxide TFT with reduced interelectrode capacitance comprising:
a transparent substrate having a front surface and a rear surface;
an opaque gate metal positioned on the front surface of the substrate and defining a gate area for a TFT;
a layer of transparent gate dielectric material positioned on the front surface of the substrate overlying the gate metal and a surrounding area;
a layer of transparent metal oxide semiconductor material positioned on the surface of the layer of transparent gate dielectric;
a layer of etch stop material positioned on the layer of metal oxide semiconductor material overlying and aligned with the gate metal, the layer of the etch stop material defining a channel area in the layer of metal oxide semiconductor material; and
conductive material patterned on the portion of the etch stop layer overlying and aligned with the gate metal and on the layer of metal oxide semiconductor material to form source and drain areas on opposed sides of the channel area.
2. A metal oxide TFT with reduced interelectrode capacitance as claimed in claim 1 wherein the layer of etch stop material includes a layer with a thickness greater than the thickness of the layer of transparent gate dielectric material.
3. A metal oxide TFT with reduced interelectrode capacitance as claimed in claim 2 wherein the layer of etch stop material thicker has a thickness greater than twice as thick as the thickness of the gate dielectric material.
4. A metal oxide TFT with reduced interelectrode capacitance as claimed in claim 2 wherein the layer of etch stop material has a thickness of at least 500 nm.
5. A metal oxide TFT with reduced interelectrode capacitance as claimed in claim 1 wherein the layer of etch stop material includes a material with a lower dielectric constant than a dielectric constant of the transparent gate dielectric material.
6. A metal oxide TFT with reduced interelectrode capacitance as claimed in claim 1 wherein the layer of transparent metal oxide semiconductor material includes one of ZnO, InO, AlZnO, ZnInO, InAlZnO, InGaSnO, InAlSnO, InGaZnO, ZnSnO, GaSnO, InGaCuO, InCuO, AlSnO, and AlCuO.
7. A metal oxide TFT with reduced interelectrode capacitance as claimed in claim 1 wherein the metal oxide TFT is included in a thin film circuit.
8. A metal oxide TFT with reduced interelectrode capacitance as claimed in claim 7 wherein the thin film circuit is included in an electronic device.