Dual-mode comparator and analog to digital converter having the same
A dual-mode comparator may include an object voltage input unit that generates a first current flowing through a first path and a second current flowing through a second path based on a first object voltage and a second object voltage, a current mirror unit that performs a current-mirror operation for the first path and the second path to output a comparison voltage at an output terminal, a bias unit that generates a bias current corresponding to a sum of the first current and the second current, and a mode switching unit that controls the current mirror unit to have a first structure in an auto-zero mode and that controls the current mirror unit to have a second structure in a comparison mode.
1. A dual-mode comparator comprising:
an object voltage input unit configured to generate a first current flowing through a first path and a second current flowing through a second path based on a first object voltage and a second object voltage;
a current mirror unit configured to perform a current-mirror operation for the first path and the second path to output a comparison voltage at an output terminal;
a bias unit configured to generate a bias current corresponding to a sum of the first current and the second current; and
a mode switching unit configured to control the current mirror unit to have a first structure in an auto-zero mode, and to control the current mirror unit to have a second structure in a comparison mode.
2. The comparator of claim 1 , wherein the object voltage input unit includes:
a first transistor configured to allow the first current to flow through the first path based on the first object voltage; and
a second transistor configured to allow the second current to flow through the second path based on the second object voltage.
3. The comparator of claim 2 , wherein the current mirror unit includes:
a third transistor coupled between a first supply voltage and the first transistor, the third transistor located on the first path; and
a fourth transistor coupled between the first supply voltage and the second transistor, the fourth transistor located on the second path.
4. The comparator of claim 3 , wherein the bias unit includes:
a fifth transistor coupled between the first and second transistors and a second supply voltage.
5. The comparator of claim 4 , wherein the mode switching unit includes:
a first switch configured to turn-on in the auto-zero mode to couple gate electrodes of the third and fourth transistors to a drain electrode of the third transistor, and configured to turn-off in the comparison mode; and
a second switch configured to turn-on in the comparison mode to couple the gate electrodes of the third and fourth transistors to a drain electrode of the fourth transistor, and configured to turn-off in the auto-zero mode.
6. The comparator of claim 5 , wherein the mode switching unit further includes:
a third switch configured to turn-on in the auto-zero mode to couple a gate electrode of the second transistor to a drain electrode of the second transistor, and configured to turn-off in the comparison mode.
7. The comparator of claim 5 , wherein the mode switching unit further includes:
a fourth switch configured to turn-on in the auto-zero mode to couple a gate electrode of the first transistor to a drain electrode of the first transistor, and configured to turn-off in the comparison mode.
8. The comparator of claim 5 , wherein the first structure is a structure in which the gate electrodes of the third and fourth transistors are coupled to the drain electrode of the third transistor, and the second structure is a structure in which the gate electrodes of the third and fourth transistors are coupled to the drain electrode of the fourth transistor.
9. The comparator of claim 8 , wherein the first and second transistors are N-type metal oxide semiconductor (NMOS) transistors, the third and fourth transistors are P-type metal oxide semiconductor (PMOS) transistors, and the fifth transistor is a NMOS transistor.
10. The comparator of claim 9 , wherein the first supply voltage corresponds to a power source voltage, and the second supply voltage corresponds to a ground voltage.
11. The comparator of claim 8 , wherein the first and second transistors are PMOS transistors, the third and fourth transistors are NMOS transistors, and the fifth transistor is a PMOS transistor.
12. The comparator of claim 11 , wherein the first supply voltage corresponds to a ground voltage, and the second supply voltage corresponds to a power source voltage.
13. An analog to digital converter comprising:
a ramp voltage generator configured to generate a ramp voltage;
a dual-mode comparator configured to,
perform an offset eliminating operation in an auto-zero mode, and
generate a comparison result signal by comparing the ramp voltage with a pixel output voltage in a comparison mode, and change a structure of the dual-mode comparator according to the auto-zero mode and the comparison mode; and
a digital signal generator configured to generate a digital signal corresponding to the pixel output voltage based on the comparison result signal.
14. The converter of claim 13 , wherein the dual-mode comparator includes:
a first comparator configured to compare the ramp voltage with the pixel output voltage to generate a first comparison voltage; and
a second comparator configured to compare the first comparison voltage with a reference voltage to generate a second comparison voltage.
15. The converter of claim 14 , wherein the second comparator includes:
an object voltage input unit configured to generate a first current flowing through a first path and a second current flowing through a second path based on the first comparison voltage and the reference voltage;
a current mirror unit configured to perform a current-mirror operation for the first path and the second path to output the second comparison voltage at an output terminal;
a bias unit configured to generate a bias current corresponding to a sum of the first current and the second current; and
a mode switching unit configured to control the current mirror unit to have a first structure in the auto-zero mode, and to control the current mirror unit to have a second structure in the comparison mode.
16. A dual-mode comparator configured to compare a first object voltage with a second object voltage, the dual-mode comparator comprising:
an object voltage input circuit configured to generate a same bias current before and after transition of at least the first object voltage from a first logic level to a second logic level.
17. The comparator of claim 16 , further comprising:
a current mirror circuit configured to switch between a first structure in a first mode and a second structure in a second mode; and
a mode switching unit configured to switch the current mirror circuit between the first and the second structures, and to output a result of the comparison.
18. The comparator of claim 16 , wherein the first mode is an auto-zero mode during which an offset between the first object voltage and the second object voltage is eliminated.
19. The comparator of claim 18 , wherein the second mode is a comparison mode during which a comparison operation is performed between the first object voltage and the second object voltage.
20. An analog to digital converter comprising:
a ramp voltage generator configured to generate a ramp voltage;
the dual-mode comparator of claim 16 , wherein the first object voltage is the ramp voltage and second object voltage is a pixel output voltage; and
a digital signal generator configured to generate a digital signal corresponding to the pixel output voltage based on the bias current generated by the dual-mode comparator.