Memory controller functionalities to support data swizzling
A memory controller that can determine a swizzling pattern between the memory controller and memory devices. The memory controller generates a swizzling map based on the determined swizzling pattern. The memory controller may internally swizzle data using the swizzling map before writing the data to memory so that the data appears in the correct order at the pins of the memory chip(s). On reads, the controller can internally de-swizzle the data before performing the error correction operations using the swizzling map.
1. A system comprising:
a memory device having a n-bit multi-purpose register (MPR); and
a memory controller coupled with the memory device, the memory controller to, for at least N combinations of N bits, wherein N is equal to the number of bits in the MPR:
write a bit combination to the MPR over a non-swizzled address bus,
read the bit combination from the MPR over a swizzled data bus, and
generate a mapping of bit ordering between the memory device and the memory controller corresponding to the swizzled data bus,
the memory controller to internally swizzle data using the mapping before writing the data to the memory so that the data appears in the correct order at pins of a memory chip, and on reads, the memory controller internally de-swizzles the data before performing error correction operations using the mapping.
2. The system of claim 1 wherein the memory device comprises a dynamic random access memory (DRAM) integrated circuit (IC) on a dual inline memory module (DIMM).
3. The system of claim 1 wherein the memory controller to, for at least N combinations of N bits, write a bit combination to the MPR comprises, for an 8-bit memory device sequentially writing a walking “0” pattern to the MPR.
4. The system of claim 1 wherein the memory controller to, for at least N combinations of N bits, write a bit combination to the MPR comprises, for an 8-bit memory device sequentially writing a walking “1” pattern to the MPR.
5. The system of claim 1 further comprising a plurality of memory devices, wherein the memory controller generates a mapping of bits between the memory controller and the plurality of memory devices for each rank of memory.
6. The system of claim 1 wherein the data written to memory comprises a 72-bit block having a 64-bit data portion rearranged by the memory controller according to the mapping and an 8-bit error correcting code (ECC) checksum.
7. The system of claim 1 wherein the memory controller further reads a block of data from the memory device and applies the mapping and error correcting code to the data read from the memory device.
8. A method of routing data in an electronics system comprising a memory device having a multi purpose register (MPR) with a plurality of bits and a memory controller coupled to the memory device, the method comprising the memory controller:
writing, for at least N combinations of N bits a bit combination to a multi-purpose register (MPR) in a memory device over a non-swizzled address bus;
reading the bit combination from the MPR over a swizzled data bus;
generating a mapping of bit ordering of the swizzled data bus between the memory device and a memory controller based on a comparison of the bit combinations written to the MPR and the corresponding bit combinations read from the MPR;
swizzling, with the memory controller using the mapping, data to be written to the memory device so that the data appears in correct order at pins of a memory chip; and
de-swizzling, on reads with the memory controller, using the mapping, the data before performing the error correction operations.
9. The method of claim 8 wherein the memory device comprises a dynamic random access memory (DRAM) integrated circuit (IC) on a dual inline memory module (DIMM).
10. The method of claim 8 wherein the at least N combinations of N bits, write a bit combination to the MPR comprises, for an 8-bit memory device sequentially writing a walking “0” pattern to the MPR, the bit combinations comprising at least:
1111 1110,
1111 1101,
1111 1011,
1111 0111,
1110 1111,
1101 1111,
1011 1111, and
0111 1111.
11. The method of claim 8 wherein least N combinations of N bits, write a bit combination to the MPR comprises, for an 8-bit memory device sequentially writing a walking “1” pattern to the MPR, the bit combinations comprising at least:
0000 0001,
0000 0010,
0000 0100,
0000 1000,
0001 0000,
0010 0000,
0100 0000,
1000 0000.
12. The method of claim 8 , in a system having multiple memory devices, further comprising generating a mapping for each memory device.
13. The method of claim 8 wherein the data written to memory comprises a 72-bit block having a 64-bit data portion rearranged by the memory controller according to the mapping and an 8-bit error correcting code (ECC) checksum.
14. The method of claim 8 further comprising reading, with the memory controller, a block of data from the memory device and applies the mapping and error correcting code to the data read from the memory device.
15. An article comprising a computer-readable medium having stored thereon, instructions that, when executed, cause a memory controller to:
write, for at least N combinations of N bits a bit combination to a multi-purpose register (MPR) in a memory device over a non-swizzled address bus;
read the bit combination from the MPR over a swizzled data bus;
generate a mapping of bit ordering of the swizzled data bus between the memory device and a memory controller based on a comparison of the bit combinations written to the MPR and the corresponding bit combinations read from the MPR; and
swizzle, with the memory controller using the mapping, data to be written to the memory device so that the data appears in correct order at pins of a memory chip; and
de-swizzle, on reads with the memory controller, using the mapping, the data before performing the error correction operations.
16. The article of claim 15 wherein the memory device comprises a dynamic random access memory (DRAM) integrated circuit (IC) on a dual inline memory module (DIMM).
17. The article of claim 15 wherein the at least N combinations of N bits, write a bit combination to the MPR comprises, for an 8-bit memory device sequentially writing a walking “0” pattern to the MPR, the bit combinations comprising at least:
1111 1110,
1111 1101,
1111 1011,
1111 0111,
1110 1111,
1101 1111,
1011 1111, and
0111 1111.
18. The article of claim 15 wherein least N combinations of N bits, write a bit combination to the MPR comprises, for an 8-bit memory device sequentially writing a walking “1” pattern to the MPR, the bit combinations comprising at least:
0000 0001,
0000 0010,
0000 0100,
0000 1000,
0001 0000,
0010 0000,
0100 0000,
1000 0000.
19. The article of claim 15 wherein the data written to memory comprises a 72-bit block having a 64-bit data portion rearranged by the memory controller according to the mapping and an 8-bit error correcting code (ECC) checksum.
20. The article of claim 15 further comprising reading, with the memory controller, a block of data from the memory device and applies the mapping and error correcting code to the data read from the memory device.