IP Library Granted Patent US 8,595,464
Granted Patent B2
US 8,595,464 · App. 13/183,164 · Granted Nov 26, 2013

Dynamic sizing of translation lookaside buffer for power reduction

Inventors: Gideon N. Levinsky (Cedar Park, TX); Manish K. Shah (Austin, TX)
Assignee: Oracle International Corporation
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Quick Facts
Patent No.
US 8,595,464
App. No.
13/183,164
Granted
Nov 26, 2013
Kind
B2
Abstract

Methods and mechanisms for operating a translation lookaside buffer (TLB). A translation lookaside buffer (TLB) includes a plurality of segments, each segment including one or more entries. A control unit is coupled to the TLB. The control unit is configured to determine utilization of segments, and dynamically disable segments in response to determining that segments are under-utilized. The control unit is also configured to dynamically enable segments responsive to determining a given number of segments are over-utilized.

Claims (51)

1. A processor, comprising:

a translation lookaside buffer (TLB) comprising a plurality of segments, wherein each segment includes one or more entries; and

a control unit coupled to the TLB, wherein the control unit is configured to:

disable an enabled segment in response to determining that the segment is under-utilized; and

enable a disabled segment in response to determining that a given number of currently-enabled segments are over-utilized;

wherein each TLB entry of the one or more entries comprises a corresponding entry access bit; and

wherein each segment of the plurality of segments further comprises a corresponding segment access bit.

2. The processor of claim 1 ,

wherein the control unit is configured to:

determine a particular segment of the plurality of segments is over-utilized, in response to determining a number of active entries in the particular segment meets an upper threshold; and

determine the particular segment of the plurality of segments is under-utilized, in response to determining the number of active entries in the particular segment meets a lower threshold.

3. The processor of claim 1 , wherein the control unit is further configured to enable a disabled segment in response to detecting an event or condition.

4. The processor of claim 3 , wherein the event comprises a TLB miss.

5. The processor of claim 1 wherein the control unit is configured to set an entry access bit of a given entry responsive to at least one of: when the entry is loaded with a translation, and when there is a valid translation match on the entry.

6. The processor of claim 1 , wherein the control unit is further configured to periodically:

set a segment access bit of a first segment if a number of set entry access bits corresponding to the first segment meets an upper threshold;

clear the segment access bit if the number of set entry access bits meets a lower threshold; and

clear all entry access bits.

7. The processor of claim 6 , wherein

a particular segment is considered over-utilized if an access bit corresponding to the particular segment is set or a number of set entry access bits corresponding to the particular segment meets an upper threshold; and

a particular segment is considered under-utilized if the access bit corresponding to the particular segment is not set and the number of set entry access bits corresponding to the particular segment meets a lower threshold.

8. A non-transitory computer readable storage medium comprising instructions, wherein the instructions are executable by a processor to:

access a translation lookaside buffer (TLB) comprising a plurality of segments, wherein each segment includes one or more entries;

disable an enabled segment in response to determining that the segment is under-utilized; and

enable a disabled segment in response to determining that a given number of currently-enabled segments are over-utilized;

wherein each TLB entry of the one or more entries comprises a corresponding entry access bit; and

wherein each segment of the plurality of segments further comprises a corresponding segment access bit.

9. The non-transitory storage medium of claim 8 , wherein the instructions are further executable by a processor to:

determine a particular segment of the plurality of segments is over-utilized, in response to determining a number of active entries in the particular segment meets an upper threshold; and

determine the particular segment of the plurality of segments is under-utilized, in response to determining the number of active entries in the particular segment meets a lower threshold.

10. The non-transitory storage medium of claim 8 , wherein the instructions are further executable by a processor to enable a disabled segment in response to detecting an event or condition.

11. The non-transitory storage medium of claim 10 , wherein the event comprises a TLB miss.

12. The non-transitory storage medium of claim 8 , wherein an entry access bit is set responsive to at least one of: when an entry is loaded with a translation, and when there is a valid translation match to an entry.

13. The non-transitory storage medium of claim 8 , wherein the instructions are further executable by a processor to:

set a segment access bit of a first segment if a number of set entry access bits corresponding to the first segment meets an upper threshold;

clear the segment access bit if the number of set entry access bits meets a lower threshold; and

clear all entry access bits.

14. The non-transitory storage medium of claim 13 , wherein

a particular segment is considered over-utilized if an access bit corresponding to the particular segment is set or a number of set entry access bits corresponding to the particular segment meets an upper threshold; and

a particular segment is considered under-utilized if the access bit corresponding to the particular segment is not set and the number of set entry access bits corresponding to the particular segment meets a lower threshold.

15. A method for managing a translation lookaside buffer (TLB), the method comprising:

accessing a translation lookaside buffer (TLB) comprising a plurality of segments, wherein each segment includes one or more entries;

disabling an enabled segment in response to determining that the segment is under-utilized; and

enabling a disabled segment in response to determining that a given number of currently-enabled segments are over-utilized;

wherein each TLB entry of the one or more entries comprises a corresponding entry access bit; and

wherein each segment of the plurality of segments further comprises a corresponding segment access bit.

16. The method of claim 15 , further comprising:

determining a particular segment of the plurality of segments is over-utilized if a number of active entries in the particular segment meets an upper threshold; and

determining a particular segment of the plurality of segments is under-utilized if a number of active entries in the particular segment meets a lower threshold.

17. The method of claim 15 , further comprising enabling a disabled segment in further response to detecting an event or condition.

18. The method of claim 17 , wherein the event comprises a TLB miss.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2011
From: LEVINSKY, GIDEON N.; SHAH, MANISH K.
To: ORACLE INTERNATIONAL CORPORATION
Reel/Frame 026599/0374 →
Continuity (1)
Related Publication 20130019080A1 · Jan 17, 2013