LCPC decoding methods and apparatus
A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.
1. An LDPC decoder, comprising:
a message source including a message output for supplying N messages in parallel, wherein N is greater than 1;
a node processing module including N node processors arranged in parallel;
a controllable permutator coupling said message source to said node processing module, said controllable permutator including a re-ordering control signal input for receiving a reordering control signal used to control reordering messages, in at least one set of N messages, being passed through said controllable permutator;
a control module for generating a first address control signal as a function of stored code description information, said control module having a first address control signal output coupled to said message source; and
a block selection module for generating a block address selection signal, said block selection module having a block address selection signal output coupled to said message source.
2. The decoder of claim 1 , wherein said control module includes:
an inner loop counter for generating said first address control signal; and
an outer loop counter for generating an outer loop control signal supplied to said block selection module, said outer loop counter being incremented as a function of an inner loop count generated by said inner loop counter.
3. The decoder of claim 2 ,
wherein said message source is a memory; and
wherein said outer loop counter is reset upon reaching a maximum count determined by a code lifting factor control signal, said control lifting factor control signal indicating a selected lifting factor, SK, SK having a value greater than or equal to 1.
4. The decoder of claim 3 , wherein said selected lifting factor SK is less than or equal to a maximum lifting K corresponding to a maximum lifting factor supported by said control module.
5. The decoder of claim 1 , wherein the block selection module includes a block ordering information signal input for receiving a block ordering information signal from said control module, said block ordering information signal being a function of a value generated by said inner counter and said stored code description information.
6. The decoder of claim 5 , wherein the message source includes an address generation module for generating a memory access signal from said first address control signal and said second address control signal.
7. The decoder of claim 6 , wherein said message source further includes a memory including at least N times K storage locations.
8. The decoder of claim 7 , wherein each of said N times K storage locations stores at least 2 bits.
9. The decoder of claim 1 , wherein the message source further includes a decompression module for decompressing messages stored in said memory prior to said messages being supplied to said controllable permutator.
10. The decoder of claim 1 , wherein each of said node processors is a variable node processor.
11. The decoder of claim 1 , wherein each of said node processors is a check node processor.
12. The decoder of claim 1 , wherein each of said node processors is a configurable node processor which is switchable between a variable node and a check node mode of operation.
13. The decoder of claim 12 , wherein each of said configurable node processors receives configuration information generated by said control module from said stored code description information.
14. A method of performing Low Density Parity Check (LDPC) decoding processing comprising:
providing a decoder including:
a memory module including N×L×K storage locations, where N and L are positive integers and K is an integer>1, each storage location being capable of storing multiple bits;
a controllable permuter coupled to said memory module for performing element re-ordering operations on a set of N multi-bit elements to change the order of the elements in said set;
a node processing module including N configurable node processors arranged in parallel coupled to said controllable permuter;
a set of stored decoder control instructions; and
generating a first re-ordering signal used to control memory access as a function of a decoder control instruction included in said set of stored decoder control instructions; and
generating a second re-ordering control signal as a function of said decoder control instruction, said second re-ordering control signal being supplied to said permuter module.
15. The method of claim 14 , further comprising:
performing a memory access operation at a location determined from said first re-ordering control signal; and
operating the permutator module to perform a message reordering operation in accordance with said supplied reordering control signal.
16. The method of claim 15 , wherein said step of performing a memory access operation at a location determined from said first re-ordering control signal includes:
generating a memory address from a first address control value included in said decoder control command and a second address control signal generated from said first re-ordering signal and a value generated by a loop counter.
17. The method of claim 16 , wherein the value generated by said loop counter is generated as a function of a codeword length indicator signal.
18. The method of claim 17 , further comprising:
configuring nodes in said node processing module as a function of configuration information included in said decoder control command.
19. An apparatus of performing Low Density Parity Check (LDPC) decoding processing comprising:
means for providing a decoder including:
a memory module including N×L×K storage locations, where N and L are positive integers and K is an integer>1, each storage location being capable of storing multiple bits;
a controllable permuter coupled to said memory module for performing element re-ordering operations on a set of N multi-bit elements to change the order of the elements in said set;
a node processing module including N configurable node processors arranged in parallel coupled to said controllable permuter;
a set of stored decoder control instructions; and
means for generating a first re-ordering signal used to control memory access as a function of a decoder control instruction included in said set of stored decoder control instructions; and
means for generating a second re-ordering control signal as a function of said decoder control instruction, said second re-ordering control signal being supplied to said permuter module.
20. The apparatus of claim 19 , further comprising:
means for performing a memory access operation at a location determined from said first re-ordering control signal; and
means for operating the permutator module to perform a message reordering operation in accordance with said supplied reordering control signal.
21. The apparatus of claim 20 , wherein said means for performing a memory access operation at a location determined from said first re-ordering control signal includes:
means for generating a memory address from a first address control value included in said decoder control command and a second address control signal generated from said first re-ordering signal and a value generated by a loop counter.
22. The apparatus of claim 21 , wherein the value generated by said loop counter is generated as a function of a codeword length indicator signal.
23. The apparatus of claim 22 , further comprising:
means for configuring nodes in said node processing module as a function of configuration information included in said decoder control command.