Enhanced diagnosis with limited failure cycles
Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example, pattern sets can be ordered according to a diagnosis coverage figure, which can be used to measure chain or logic diagnosability of the pattern set. Per-pin based diagnosis techniques can also be used to analyze limited failure data.
1. A method for diagnosing defects in a circuit, comprising:
receiving information from multiple tester channels indicative of failing test responses produced by the circuit in response to one or more test patterns, the information including an indication that test response data from one or more of the test channels is truncated for one or more of the test patterns;
simulating one or more of the test patterns being loaded into scan chains and applied to system logic sections of the circuit, the simulation comprising modifying values in scan cells associated with the one or more truncated test channels;
determining a range of one or more fault candidates based at least in part on the simulation; and
storing the range of the one or more fault candidates.
2. The method of claim 1 , wherein at least some of the values are modified based at least in part on a determined fault type.
3. The method of claim 1 , wherein at least some of the values are modified to unknown values.
4. The method of claim 1 wherein the range includes the last scan cell in a corresponding scan chain.
5. The method of claim 1 further comprising repeating the act of simulating but modifying only values within the range.
6. The method of claim 5 , further comprising:
determining a revised range of one or more fault candidates based at least in part on the repeated simulation; and
storing the fault candidates from the revised range.
7. The method of claim 1 , wherein the information received comprises a pin-based failure log.
8. A diagnostic system configured to perform the method of claim 1 .
9. A non-transitory computer-readable storage medium storing computer-executable instructions which when executed by a computer cause the computer to perform a method, the method comprising:
receiving information from multiple tester channels indicative of failing test responses produced by the circuit in response to one or more test patterns, the information including an indication that test response data from one or more of the test channels is truncated for one or more of the test patterns;
simulating one or more of the test patterns being loaded into scan chains and applied to system logic sections of the circuit, the simulation comprising modifying values in scan cells associated with the one or more truncated test channels;
determining a range of one or more fault candidates based at least in part on the simulation; and
storing the range of the one or more fault candidates.
10. The non-transitory computer-readable medium of claim 9 , wherein at least some of the values are modified based at least in part on a determined fault type.
11. The non-transitory computer-readable medium of claim 9 , wherein at least some of the values are modified to unknown values.
12. The non-transitory computer-readable medium of claim 9 , wherein the range includes the last scan cell in a corresponding scan chain.
13. The non-transitory computer-readable medium of claim 9 , further comprising repeating the act of simulating but modifying only values within the range.
14. The non-transitory computer-readable medium of claim 13 , further comprising:
determining a revised range of one or more fault candidates based at least in part on the repeated simulation; and
storing the fault candidates from the revised range.