Integrated circuit having pitch reduced patterns relative to photoithography features
An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.
1. An integrated circuit comprising: an integrated circuit substrate; a circuit pattern with a peripheral outer region and an inner region wherein a first set of features is located in the peripheral outer region and a second set of features is located in the inner region wherein at least a portion of the
first set of features has a dimension greater than about 100 nm and at least a portion of the second set of features has
a dimension less than about 100 nm, wherein the dimension of the second feature is a pitch multiple of the dimension of the first feature.
2. The integrated circuit of claim 1 wherein the substrate is a semiconductor substrate on which is formed:
a silicide layer; a first polysilicon layer; an oxide-nitride-oxide layer; and a second polysilicon layer.
3. The integrated circuit of claim 1 wherein the circuit pattern is a random access memory circuit
comprising memory cells in the inner region comprising a second set of features and logic circuits in the peripheral
outer region comprising the first set of features.
4. The integrated circuit of claim 1
wherein at least one of the first set of features is a control gate stack.
5. The integrated circuit of claim 1 wherein at least one of the first set of features is a landing pad and wherein at least one of the second sets of features is series of lines and spaces.
6. The integrated circuit of claim 1 wherein features with the dimension of the first set of features are not located in the inner region and features with the dimensions of the second set of features are not located in the peripheral outer region.