Digital delay-locked loop with drift sensor
Embodiments of the present disclosure provide methods, systems, and apparatuses related to an open-loop digital delay-locked loop having a drift sensor. Other embodiments may be described and claimed.
1. A circuit comprising:
a delay line configured to receive a first signal and to output a delayed version of the first signal, the delay line having a plurality of delay elements serially coupled with one another;
a drift sensor configured to receive a sensor input signal, which is either the first signal or the delayed version of the first signal, and to selectively output, as a sensor output signal, the sensor input signal or a delayed version of the sensor input signal; and
a phase detector coupled with the delay line and the drift sensor and configured to output a phase detector signal based on a phase relationship between two phase detector input signals.
2. The circuit of claim 1 , further comprising:
a state machine coupled with the phase detector, the drift sensor, and the delay line, the state machine configured to:
provide a first control signal to the delay line to adjust an amount of delay provided by the plurality of delay elements, and
provide a second control signal to the drift sensor to control selective output of the sensor input signal or the delayed version of the sensor input signal as the sensor output signal.
3. The circuit of claim 2 , wherein the first control signal and the second control signal are digital control signals.
4. The circuit of claim 1 , further comprising:
a state machine coupled with the drift sensor and the delay line and configured to lock an amount of delay provided by the delay line and, while the amount of delay is locked, to control the drift sensor to output the sensor input signal, as the sensor output signal, when the phase detector signal is a first value and to output the delayed version of the sensor input signal, as the sensor output signal, when the phase detector signal is a second value.
5. The circuit of claim 1 , further comprising:
a state machine coupled with the delay line, the state machine having a counter configured to increment every clock cycle in which the phase detector signal is a first value.
6. The circuit of claim 5 , wherein the state machine is configured to:
compare the counter to a threshold value; and
adjust an amount of delay provided by the delay line based on comparison of the counter to the threshold value.
7. The circuit of claim 6 , wherein the state machine is configured to incrementally adjust an amount of delay provided by the delay line until the phase detector signal switches from the first value to a second value.
8. The circuit of claim 5 , wherein the counter is configured to be decremented every clock cycle in which the phase detector signal has a second value.
9. The circuit of claim 1 , wherein the drift sensor comprises a delay element configured to receive the sensor input signal and to output the delayed version of the sensor input signal, wherein a delay provided by the delay element is larger than a least-significant adjustment interval of the delay line.
10. A method comprising:
tracking, while a state machine is in a locked phase, values of a phase detector signal, wherein the values indicate a phase relationship between two phase detector input signals;
outputting a sensor input signal as a first phase detector input signal based on a first value of the phase detector signal and outputting a delayed version of the sensor input signal as the first phase detector input signal based on a second value of the phase detector signal; and
entering a calibration phase, based on said tracking, to adjust a delay provided by a delay line.
11. The method of claim 10 , wherein the delay of the delay line is locked while the state machine is in the locked phase.
12. The method of claim 10 , further comprising:
providing a delayed version of an oscillator signal as the sensor input signal;
providing the oscillator signal a second phase detector input signal.
13. The method of claim 10 , further comprising:
providing a delayed version of an oscillator signal, from the delay line, as a second phase detector input signal; and
providing the oscillator signal as the sensor input signal.
14. The method of claim 10 , wherein said tracking comprises:
incrementing a counter every clock cycle in which the phase detector signal has the first value;
comparing the counter to a threshold value; and
entering the calibration phase based on said comparing.
15. The method of claim 10 , further comprising:
generating a first digital control signal to adjust the delay provided by the delay line; and
generating a second digital control signal to control a drift sensor to output the sensor input signal or the delayed version of the sensor input signal.
16. A system comprising:
a delay-locked loop (DLL) having:
a delay line having a plurality of delay elements;
a drift sensor configured to selectively output either a sensor input signal or a delayed version of the sensor input signal to facilitate detection of a negative or positive drift in a delay provided by the delay line; and
a plurality of phase outputs respectively coupled with the plurality of delay elements;
a clock generation circuit coupled with the DLL and configured to generate a multi-phase clocking signal based on the plurality of phase outputs; and
a wireless network interface controller coupled with the clock generation circuit and configured to modulate signals to be communicated over a wireless network based on the multi-phase clocking signal.
17. The system of claim 16 , wherein the DLL further comprises:
a state machine configured to detect the drift based on a detection that a phase detector signal has a first value for a predetermined number of clock cycles, wherein the first value is indicative of a phase relationship between two phase detector input signals.
18. The system of claim 17 , wherein the state machine comprises a counter configured to increment every clock cycle in which the phase detector signal has the first value and to be decremented every clock cycle in which the phase detector signal has a second value.
19. The system of claim 17 , wherein the DLL further comprises:
a state machine configured to:
provide a first control signal to the delay line to adjust amount of delay provided by the plurality of delay elements, and
provide a second control signal to the drift sensor to control selective output of the sensor input signal or the delayed version of the sensor input signal as a phase detector input signal.
20. The system of claim 19 , wherein the first control signal and the second control signal are digital control signals.