Method and apparatus for improving noise power estimate in WCDMA network
Method and apparatus for improving a noise power estimate in a wideband CDMA (WCDMA) network are disclosed and may include calculating a total noise power estimate for a downlink channel based on a plurality of control channel bits from a plurality of different types of control channels. The plurality of control channel bits may include at least two of: dedicated physical channel (DPCH) transmit power control (TPC) bits, DPCH pilot bits, and common pilot channel (CPICH) bits. A first noise power estimate may be calculated for the downlink channel based on a plurality of the DPCH TPC bits. A value of at least one of the plurality of DPCH TPC bits may not be known when the at least one of the plurality of DPCH TPC bits is received.
1. A method for signal processing, the method comprising calculating, a total noise power estimate for a downlink channel based on a plurality of control channel bits received via a plurality of different types of control channels, wherein said calculating said total noise power estimate comprises calculating a first noise power estimate for said downlink channel based on a plurality of dedicated physical channel (DPCH) transmit power control (TPC) bits, and wherein a value of at least one of said plurality of DPCH TPC bits is not known when said at least one of said plurality of DPCH TPC bits is received.
2. The method according to claim 1 , wherein said calculating said total noise power estimate further comprises calculating a second noise power estimate for said downlink channel based on a plurality of DPCH pilot bits.
3. The method according to claim 2 , wherein said calculating said total noise power estimate further comprises calculating said total noise power estimate for said downlink channel based on said calculated first noise power estimate and said calculated second noise power estimate.
4. The method according to claim 3 , wherein said calculating said total noise power estimate further comprises:
scaling said calculated second noise power estimate utilizing a scaling factor that is a function of a number of TPC bits per slot to yield a scaled second noise power estimate; and
summing said first noise power estimate and said scaled second noise power estimate to yield said total noise power estimate.
5. The method, according to claim 2 , wherein said calculating said total noise power estimate further comprises calculating a third noise power estimate for said downlink channel based on a plurality of common pilot channel (CPICH) bits.
6. The method according to claim 5 , wherein said calculating said total noise power estimate further comprises calculating said total noise power estimate for said downlink channel based on said calculated first noise power estimate, said calculated second noise power estimate, and said calculated third noise power estimate.
7. The method according to claim 1 , wherein said calculating said first noise power estimate comprises summing portions of said plurality of DPCH TPC bits that are received via said downlink channel to generate an in-phase (I) component and a quadrature (Q) component.
8. The method according to claim 7 , wherein said calculating said first not se power estimate further comprises:
subtracting said generated I component and said generated Q component to determine said first noise power estimate for said downlink channel; and
squaring said subtracted I component and said generated Q component to determine said first noise power estimate for said downlink channel.
9. The method according to claim 8 , wherein said calculating said first noise power estimate further comprises:
summing said squared I component and said generated Q component over a plurality of TPC symbols to determine said first noise power estimate for said downlink channel,
wherein said plurality of TPC symbols is one half of said plurality of DPCH TPC bits per slot of said downlink channel.
10. The method according to claim 9 , wherein said calculating said first noise power estimate further comprises:
calculating a norm of said summed I component and said generated Q component by dividing said sum of said squared I component and said generated Q component by a number of said plurality of DPCH TPC bits per slot of said downlink channel to determine said first noise power estimate for said downlink channel wherein said plurality of TPC symbols is one half of said plurality of DPCH TPC bits per slot of said downlink channel.
11. The method according to claim 2 , wherein said calculating said second noise power estimate further comprises:
calculating a mean of a plurality of DPCH pilot bits that are received via said downlink channel to yield a mean square estimate;
calculating a mean of a power of said plurality of DPCH pilot bits that are received via said downlink channel to yield a mean power estimate; and
subtracting said mean square estimate from said mean power estimate to determine said second noise power estimate for said downlink channel.
12. The method according to claim 1 , further comprising adjusting transmit power of a transmitter when said transmitter communicates via said downlink channel based on said total noise power estimate.
13. A system for signal processing, the system comprising a circuitry configured to calculate a total noise power estimate for a downlink channel based on a plurality of control channel bits received via a plurality of different types of control channels, wherein said circuitry is configured to calculate a first noise power estimate for said downlink channel based on a plurality of dedicated physical channel (DPCH) transmit power control (TPC) bits, and wherein a value of at least one of said plurality of DPCH TPC bits is not known when said at least one of said plurality of DPCH TPC bits is received.
14. The system according to claim 13 , wherein said circuitry is configured to calculate a second noise power estimate for said downlink channel based on a plurality of DPCH pilot bits.
15. The system according to claim 14 , wherein said circuitry is configured to calculate said total noise power estimate for said downlink channel based on said calculated first noise power estimate and said calculated second noise power estimate.
16. The system according to claim 15 , wherein:
said circuitry is configured to scale said calculated second noise power estimate utilizing a scaling factor that is a function of a number of TPC bits per slot to yield a scaled second noise power estimate; and
said circuitry is configured to sum said first noise power estimate and said scaled second noise power estimate to yield said total noise power estimate.
17. The system according to claim 14 , wherein said circuitry is configured to calculate a third noise power estimate for said downlink channel based on a plurality of common pilot channel (CPICH) bits.
18. The system according to claim 17 , wherein said circuitry is configured to calculate said total noise power estimate for said downlink channel based on said calculated first noise power estimate, said calculated second noise power estimate, and said calculated third noise power estimate.
19. The system according to claim 13 , wherein said circuitry is configured to sum portions of a plurality of DPCH TPC bits that are received via said downlink channel to generate an in-phase (I) component and a quadrature (Q) component.
20. The system according to claim 19 , wherein:
said circuitry is configured to subtract said generated I component and said generated Q component to determine said first noise power estimate for said downlink channel; and
said circuitry is configured to square said subtracted I component and said generated Q component to determine said first noise power estimate for said downlink channel.
21. The system according to claim 20 , wherein said circuitry is configured to sum said squared I component and said generated Q component over a plurality of TPC symbols to determine said first noise power estimate for said downlink channel wherein said plurality of TPC symbols is one half of said plurality of DPCH TPC bits per slot of said downlink channel.
22. The system according to claim 21 , wherein said circuitry is configured to calculate a norm of said summed I component and said generated Q component by dividing said sum of said squared I component and said generated Q component by a number of said plurality of DPCH TPC bits per slot of said downlink channel to determine said first noise power estimate for said downlink channel, and wherein said plurality of TPC symbols is one half of said plurality of DPCH TPC bits per slot of said downlink channel.
23. The system according to claim 14 , wherein:
said circuitry is configured to calculate a mean of a plurality of DPCH pilot bits that are received via said downlink channel to yield a mean square estimate; and
said circuitry is configured to calculate a mean of a power of said plurality of DPCH pilot bits that are received via said downlink channel to yield a mean power estimate,
wherein said circuitry is configured to subtract said mean square estimate from said mean power estimate to determine said second noise power estimate for said downlink channel.
24. The system according to claim 13 , wherein said circuitry is configured to adjust transmit power of a transmitter when said transmitter communicates via said downlink channel based on said total noise power estimate.
25. A method comprising:
receiving a plurality of control channel bits via a plurality of different types of control channels;
calculating a first noise power estimate for a downlink channel based on a plurality of dedicated physical channel (DPCH) transmit power control (TPC) bits, wherein a value of at least one of said plurality of DPCH TPC bits is not known, when said at least one of said plurality of DPCH TPC bits is received;
calculating a second noise power estimate for said downlink channel based on a plurality of DPCH pilot bits; and
calculating a total noise power estimate for a downlink channel based on said first noise power estimate and said second noise power estimate.
26. A system for signal processing, the system comprising a circuitry configured to:
calculate a first noise power estimate for said downlink channel based on a plurality of dedicated physical channel (DPCH) transmit power control (TPC) bits by summing portions of a plurality of DPCH TPC bits that are received via a downlink channel, to generate an in-phase (I) component and a quadrature (Q) component, and
calculate a total noise power estimate for said downlink channel based on said first noise power estimate and a plurality of control channel bits received via a plurality of different types of control channels.
27. A method comprising:
receiving a plurality of control channel bits via a plurality of different types of control channels;
calculating a first noise power estimate for a downlink channel based on a plurality of dedicated physical channel (DPCH) transmit power control (TPC) bits, wherein said calculating said first noise power estimate comprises summing portions of said plurality of DPCH TPC bits that are received via said downlink channel to generate an in-phase (I) component and a quadrature (Q) component;
calculating a second noise power estimate for said downlink channel based on a plurality of DPCH pilot bits; and
calculating a total noise power estimate for a downlink channel based on said first noise power estimate and said second noise power estimate.