Heterojunction field-effect transistor with field plate connected to gate or source electrode

1. A field effect transistor, comprising:

a substrate;

a first group III nitride semiconductor layer formed on the substrate;

a second group III nitride semiconductor layer formed on the first group III nitride semiconductor layer, and having a band gap wider than that of the first group III nitride semiconductor layer;

a source electrode and a drain electrode formed on the second group III nitride semiconductor layer, and a gate electrode formed between the source electrode and the drain electrode; and

a field plate formed on the second group III nitride semiconductor layer to be connected to the gate electrode or the source electrode, and to cover an edge of the gate electrode closer to the drain electrode, wherein

the first group III nitride semiconductor layer has a low carbon concentration region having a carbon concentration of less than 1×10 17 cm −3 , and located in at least a region under the edge of the gate electrode closer to the drain electrode,

a thickness d 2 (μm) of the low carbon concentration region satisfies

V m /(110 ·d 1)≦ d 2< V m /(110 ·d 1)+0.5

where d 1 (μm) is a thickness of a group III nitride semiconductor layer including the first group III nitride semiconductor layer and the second group III nitride semiconductor layer, and V m (V) is an operating breakdown voltage, and

a ratio of R on to R on0 , which is an index of a current collapse value, satisfies

R on /R on0 ≦3

where R on0 is an on-state resistance in a relaxed state, and R on is an on-state resistance measured 100 μs after a transition from an off state to an on state under an operating voltage V m .

2. The field effect transistor of claim 1 , wherein

the thickness of the low carbon concentration region of the first group III nitride semiconductor layer is uneven, and a part of the low carbon concentration region located under an edge of the field plate closer to the drain electrode has a maximum thickness.

3. The field effect transistor of claim 2 , wherein

a part of the low carbon concentration region located under a position closer to the source electrode has a minimum thickness.

4. The field effect transistor of claim 1 , wherein

an increased-resistance region into which an impurity for improving insulation properties of the first group III nitride semiconductor layer is added is formed in a region of the low carbon concentration region located under a region extending from a middle portion of the gate electrode to a portion of the gate electrode closer to the source electrode along a gate length direction.

5. The field effect transistor of claim 4 , wherein

the impurity is at least one of iron, boron, magnesium, zinc, or rubidium.

6. The field effect transistor of claim 1 , further comprising

one or more buffer layers formed between the substrate and the first group III nitride semiconductor layer.

7. The field effect transistor of claim 6 , wherein

the one or more buffer layers are sequentially formed on the substrate, and include a first buffer layer, a second buffer layer, and a third buffer layer each made of a group III nitride semiconductor.

8. The field effect transistor of claim 7 , wherein

E g1 , E g2 , and E g3 satisfy

E g1 >E g2 >E g3

where E g1 is a band gap of the first buffer layer, E g2 is a band gap of the second buffer layer, and E g3 is a band gap of the third buffer layer.

9. The field effect transistor of claim 6 , wherein

a carbon concentration of each of the one or more buffer layers is 10 18 cm −3 or more.

10. The field effect transistor of claim 6 , wherein

a carbon concentration of each of the one or more buffer layers is 10 19 cm −3 or more and 10 21 cm −3 or less.