High breakdown voltage embedded MIM capacitor structure
Methods and devices related to a plurality of high breakdown voltage embedded capacitors are presented. A semiconductor device may include gate material embedded in an insulator, a plurality of metal contacts, and a plurality of capacitors. The plurality of capacitors may include a lower electrode, a dielectric formed so as to cover a surface of the lower electrode, and an upper electrode formed on the dielectric. Further, the plurality of contacts may connect each of the lower electrodes of the plurality of capacitors to the gate material. The plurality of capacitors may be connected in series via the gate material.
1. A semiconductor device, comprising:
gate material embedded in an insulator; and
first and second capacitors, each capacitor comprising: a lower electrode; a dielectric formed so as to cover the surface of the lower electrode; and an upper electrode formed on the dielectric, wherein the lower electrode, dielectric, and upper electrode are well-type structures, and
wherein metal contacts couple the lower electrode of each of the first and second capacitors to a first gate material, and wherein the first and second capacitors are connected in series via the first gate material;
third and fourth capacitors, each capacitor comprising: a lower electrode; a dielectric formed so as to cover the surface of the lower electrode; and an upper electrode formed on the dielectric and
wherein metal contacts couple the lower electrode of each of the third and fourth capacitors to a second gate material, wherein the third and fourth capacitors are connected in series via a second gate material, and
wherein the upper electrodes of the second capacitor and the fourth capacitor share a common metal portion, and wherein the common metal portion is electrically coupled to a first voltage terminal through a first metal plate; and
wherein the upper electrodes of the first capacitor and the third capacitor are electrically coupled to a second voltage terminal through a second metal plate.
2. The semiconductor device of claim 1 , wherein the gate material includes a first layer and a second layer.
3. The semiconductor device of claim 2 , wherein the first layer of the gate material is a NiSi material.
4. The semiconductor device of claim 2 , wherein the second layer of the gate material is a n+ doped material.
5. The semiconductor device of claim 2 , wherein the second layer of the gate material is a p+ doped material.
6. The semiconductor device of claim 1 , wherein the gate material is formed on a first insulating layer and wherein the gate material is at least three times thicker than the first insulating layer.
7. The semiconductor device of claim 1 , wherein the capacitors are a metal insulator metal (MIM) capacitor type.
8. The semiconductor device of claim 1 , wherein the dielectric is of a high k dielectric type.
9. The semiconductor device of claim 1 , further comprising a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the semiconductor device is integrated.
10. A semiconductor device comprising:
means for insulating a gate material;
first and second capacitors, each comprising: a lower electrode; a dielectric formed so as to cover a surface of the lower electrode; and an upper electrode formed on the dielectric, wherein the lower electrode, dielectric, and upper electrode are well-type structures; and
means for coupling each of the first and second capacitors to a first gate material, wherein the first and second capacitors are connected in series via the first gate material;
third and fourth capacitors, each capacitor comprising: a lower electrode; a dielectric formed so as to cover the surface of the lower electrode; and an upper electrode formed on the dielectric and
means for coupling each of the third and fourth capacitors to a second gate material, wherein the third and fourth capacitors are connected in series via the second gate material; and
wherein the upper electrodes of the second capacitor and the fourth capacitor share a common metal portion, and wherein the common metal portion is electrically coupled to a first voltage terminal through a first coupling means; and
wherein the upper electrodes of the first capacitor and the third capacitor are electrically coupled to a second voltage terminal through a second coupling means.
11. The semiconductor device of claim 10 , wherein the gate material includes a first layer and a second layer.
12. The semiconductor device of claim 11 , wherein the first layer of the gate material is a NiSi material.
13. The semiconductor device of claim 11 , wherein the second layer of the gate material is a n+ doped material.
14. The semiconductor device of claim 11 , wherein the second layer of the gate material is a p+ doped material.
15. The semiconductor device of claim 10 , wherein the gate material is formed on a first insulating layer and wherein the gate material is at least three times thicker than the first insulating layer.
16. The semiconductor device of claim 1 , wherein the first voltage terminal is a common or ground source, and the second voltage terminal is a positive voltage source.
17. The semiconductor device of claim 1 , wherein the series connection of the first and second capacitors is connected in parallel to the series connection of the third and fourth capacitors.
18. The semiconductor device of claim 1 , wherein the first and second metal plates are orthogonal to the upper electrodes of the first, second, third, and fourth capacitors.
19. The semiconductor device of claim 18 , wherein a plurality of capacitors are interconnected by the first and second metal plates to the first, second, third, and fourth capacitors, such that the plurality of capacitors and the first, second, third, and fourth capacitors form an array of capacitors.