Through silicon via keep out zone formation along different crystal orientations
Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.
1. An integrated circuit (IC), comprising:
an active device;
a first through silicon via (TSV);
a first keep out zone (KOZ) defined as a region wherein a stress impact caused by the first TSV exceeds a first threshold throughout the entire region, wherein the first KOZ has a first radius to a center of the first TSV in a first crystal orientation and a second radius to the center of the first TSV in a second orientation, the first radius being smaller than the second radius; and
wherein no active device is placed within the first KOZ.
2. The IC of claim 1 , further comprising a second KOZ defined as a second region where the stress impact caused by the first TSV exceeds a second threshold throughout the entire region; and
wherein no active device is placed within the second KOZ.
3. The IC of claim 1 , wherein the first KOZ is from about 10 μm to about 20 μm.
4. The IC of claim 1 , wherein the first threshold is a percentage of drain current shift caused by the first TSV.
5. The IC of claim 1 , wherein the first threshold is a mobility change percentage caused by the first TSV.
6. The IC of claim 2 , wherein the second threshold is a critical dimension of the first TSV, or a pitch of first the TSV to another adjacent TSV.
7. The IC of claim 4 , wherein the percentage is from about 10% to about 20%.
8. The IC of claim 1 , wherein the first KOZ has a smallest radius in a crystal orientation among all orientations.
9. The IC of claim 1 , further comprising an additional TSV placed outside of the first KOZ and located relative to the first TSV in a crystal orientation at which the first KOZ has a least radius to the center of the first TSV, wherein an additional KOZ of the additional TSV and the first KOZ are disjoint.
10. The IC of claim 9 , further comprising a third TSV adjacent the additional TSV, outside of the additional KOZ, and located relative to the additional TSV in a direction at which the additional KOZ has a least radius to a center of the additional TSV, wherein a KOZ of the third TSV, the additional KOZ, and the first KOZ are disjoint.
11. The IC of claim 9 , wherein the additional TSV is placed along a crystal orientation at which the first KOZ has the least radius to the center of the first TSV.
12. The IC of claim 9 , further comprising two more TSVs wherein the TSV, the additional TSV, and the two more TSVs form a diamond shape along a crystal orientation in which the first KOZ has the least radius to the center of the first TSV.
13. The IC of claim 1 , wherein the active device is a n-type transistor or a p-type transistor.
14. The IC of claim 1 , further comprising:
a plurality of TSVs, the first TSV being one of the plurality of TSVs, the plurality of TSVs forming a regular shape, wherein each TSV has a respective KOZ and an overall KOZ for the plurality of TSVs is formed by union the respective KOZ of each TSV; and
a plurality of TSV stress plugs formed at a perimeter of the overall KOZ of the plurality of TSVs; and wherein
no active device of the IC is located within the overall KOZ.
15. The IC of claim 14 , wherein a respective KOZ size of the first TSV is determined by a first method and a respective KOZ size of a second TSV is determined by a second method.
16. The IC of claim 14 , wherein the plurality of TSV stress plugs is formed in a same process as forming the plurality of TSVs.
17. The IC of claim 14 , wherein the plurality of TSVs form a linear array and the plurality of TSV stress plugs are formed at ends of the linear array.
18. The IC of claim 14 , wherein the plurality of TSVs form a circle and the plurality of TSV stress plugs are formed at alternating positions within the circle.
19. The IC of claim 14 , where the plurality of TSVs form a T-shape having three end points and the plurality of TSV stress plugs are formed at the three end points.