IP Library › Granted Patent US 8,605,073
Granted Patent B2
US 8,605,073 · App. 13/026,863 · Granted Dec 10, 2013

Pulse signal output circuit and shift register

Inventors: Atsushi Umezaki (Kanagawa, JP); Hajime Kimura (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 8,605,073
App. No.
13/026,863
Granted
Dec 10, 2013
Kind
B2
Abstract

A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/μm (1×10 −18 A/μm) or less. Therefore, the drive capability of the semiconductor device can be improved.

Claims (75)

1. A display device comprising:

a plurality of gate signal lines;

a plurality of source signal lines;

a pixel provided in a region where the gate signal line and the source signal line intersect with each other; and

a gate driver circuit directly electrically connected to the plurality of gate signal lines,

wherein the gate driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an inverter circuit,

wherein a first terminal of the first transistor is directly electrically connected to a first wiring, and a second terminal of the first transistor is directly electrically connected to a second wiring,

wherein a first terminal of the second transistor is directly electrically connected to a third wiring, and a second terminal of the second transistor is directly electrically connected to the second wiring,

wherein a first terminal of the third transistor is directly electrically connected to a fourth wiring, a second terminal of the third transistor is directly electrically connected to a gate of the first transistor, and a gate of the third transistor is directly electrically connected to the fourth wiring,

wherein a first terminal of the fourth transistor is directly electrically connected to the third wiring, a second terminal of the fourth transistor is directly electrically connected to the gate of the first transistor, and a gate of the fourth transistor is directly electrically connected to a fifth wiring,

wherein an input terminal of the inverter circuit is directly electrically connected to the gate of the first transistor, and an output terminal of the inverter circuit is directly electrically connected to a gate of the second transistor,

wherein a channel region of each of the first to fourth transistors includes an oxide semiconductor, and

wherein off-state current of each of the first to fourth transistors is 1 aA/μm or less.

2. An electronic device comprising the display device according to claim 1 and an operation switch configured to control an image of the display device.

3. A display device comprising:

a plurality of gate signal lines;

a plurality of source signal lines;

a pixel provided in a region where the gate signal line and the source signal line intersect with each other; and

a gate driver circuit directly electrically connected to the plurality of gate signal lines,

wherein the gate driver circuit includes a first transistor, a second transistor, a third transistor, and an inverter circuit,

wherein a first terminal of the first transistor is directly electrically connected to a first wiring, and a second terminal of the first transistor is directly electrically connected to a second wiring,

wherein a first terminal of the second transistor is directly electrically connected to a third wiring, and a second terminal of the second transistor is directly electrically connected to the second wiring,

wherein a first terminal of the third transistor is directly electrically connected to the second wiring, a second terminal of the third transistor is directly electrically connected to a gate of the first transistor, and a gate of the third transistor is directly electrically connected to the first wiring,

wherein an input terminal of the inverter circuit is directly electrically connected to the gate of the first transistor, and an output terminal of the inverter circuit is directly electrically connected to a gate of the second transistor,

wherein a channel region of each of the first to third transistors includes an oxide semiconductor, and

wherein off-state current of each of the first to third transistors is 1 aA/μm or less.

4. A display device comprising:

a plurality of gate signal lines;

a plurality of source signal lines;

a pixel provided in a region where the gate signal line and the source signal line intersect with each other; and

a gate driver circuit directly electrically connected to the plurality of gate signal lines,

wherein the gate driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an inverter circuit,

wherein a first terminal of the first transistor is directly electrically connected to a first wiring, and a second terminal of the first transistor is directly electrically connected to a second wiring,

wherein a first terminal of the second transistor is directly electrically connected to a third wiring, and a second terminal of the second transistor is directly electrically connected to the second wiring,

wherein a first terminal of the third transistor is directly electrically connected to a fourth wiring, a second terminal of the third transistor is directly electrically connected to a gate of the first transistor, and a gate of the third transistor is directly electrically connected to the fourth wiring,

wherein a first terminal of the fourth transistor is directly electrically connected to the second wiring, a second terminal of the fourth transistor is directly electrically connected to the gate of the first transistor, and a gate of the fourth transistor is directly electrically connected to the first wiring,

wherein an input terminal of the inverter circuit is directly electrically connected to the gate of the first transistor, and an output terminal of the inverter circuit is directly electrically connected to a gate of the second transistor,

wherein a channel region of each of the first to fourth transistors includes an oxide semiconductor, and

wherein off-state current of each of the first to fourth transistors is 1 aA/μm or less.

5. A display device comprising:

a plurality of gate signal lines;

a plurality of source signal lines;

a pixel provided in a region where the gate signal line and the source signal line intersect with each other; and

a gate driver circuit directly electrically connected to the plurality of gate signal lines, wherein the gate driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an inverter circuit,

wherein a first terminal of the first transistor is directly electrically connected to a first wiring, and a second terminal of the first transistor is directly electrically connected to a second wiring,

wherein a first terminal of the second transistor is directly electrically connected to a third wiring, and a second terminal of the second transistor is directly electrically connected to the second wiring,

wherein a first terminal of the third transistor is directly electrically connected to the third wiring, a second terminal of the third transistor is directly electrically connected to a gate of the first transistor, and a gate of the third transistor is directly electrically connected to a fourth wiring,

wherein a first terminal of the fourth transistor is directly electrically connected to the second wiring, a second terminal of the fourth transistor is directly electrically connected to the gate of the first transistor, and a gate of the fourth transistor is directly electrically connected to the first wiring,

wherein an input terminal of the inverter circuit is directly electrically connected to the gate of the first transistor, and an output terminal of the inverter circuit is directly electrically connected to a gate of the second transistor,

wherein a channel region of each of the first to fourth transistors includes an oxide semiconductor, and

wherein off-state current of each of the first to fourth transistors is 1 aA/μm or less.

6. A display device comprising:

a plurality of gate signal lines;

a plurality of source signal lines;

a pixel provided in a region where the gate signal line and the source signal line intersect with each other; and

a gate driver circuit directly electrically connected to the plurality of gate signal lines,

wherein the gate driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and an inverter circuit,

wherein a first terminal of the first transistor is directly electrically connected to a first wiring, and a second terminal of the first transistor is directly electrically connected to a second wiring,

wherein a first terminal of the second transistor is directly electrically connected to a third wiring, and a second terminal of the second transistor is directly electrically connected to the second wiring,

wherein a first terminal of the third transistor is directly electrically connected to a fourth wiring, a second terminal of the third transistor is directly electrically connected to a gate of the first transistor, and a gate of the third transistor is directly electrically connected to the fourth wiring,

wherein a first terminal of the fourth transistor is directly electrically connected to the third wiring, a second terminal of the fourth transistor is directly electrically connected to the gate of the first transistor, and a gate of the fourth transistor is directly electrically connected to a fifth wiring,

wherein a first terminal of the fifth transistor is directly electrically connected to the second wiring, a second terminal of the fifth transistor is directly electrically connected to the gate of the first transistor, and a gate of the fifth transistor is directly electrically connected to the first wiring,

wherein an input terminal of the inverter circuit is directly electrically connected to the gate of the first transistor, and an output terminal of the inverter circuit is directly electrically connected to a gate of the second transistor,

wherein a channel region of each of the first to fifth transistors includes an oxide semiconductor, and

wherein off-state current of each of the first to fifth transistors is 1 aA/μm or less.

7. A display device comprising:

a plurality of gate signal lines;

a plurality of source signal lines;

a pixel provided in a region where the gate signal line and the source signal line intersect with each other; and

a gate driver circuit directly electrically connected to the plurality of gate signal lines, wherein the gate driver circuit includes a first transistor, a second transistor, and an inverter circuit,

wherein a first terminal of the first transistor is directly electrically connected to a first wiring, and a second terminal of the first transistor is directly electrically connected to a second wiring

wherein a first terminal of the second transistor is directly electrically connected to a third wiring, and a second terminal of the second transistor is directly electrically connected to the second wiring,

wherein an input terminal of the inverter circuit is directly electrically connected to a gate of the first transistor, and an output terminal of the inverter circuit is directly electrically connected to a gate of the second transistor,

wherein a channel region of each of the first transistor and the second transistor includes an oxide semiconductor, and

wherein off-state current of each of the first transistor and the second transistor is 1 aA/μm or less.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2011
From: UMEZAKI, ATSUSHI; KIMURA, HAJIME
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 025878/0154 →
Priority Claims (1)
JP 2010-033669 · Feb 18, 2010 · national
Continuity (1)
Related Publication 20110199365A1 · Aug 18, 2011