Verification module apparatus to serve as a prototype for functionally debugging an electronic design that exceeds the capacity of a single FPGA

1. A system for designing and emulating a user design, which system comprises:

(i) a verification module and system controller comprising: (a) an interface to a user workstation; (b) at least one field programmable logic device configured as an conventional embedded logic analyzer IP circuit description; and (c) at least one first clock and user signal compression tunnel portal; and

(ii) at least one SoC partition logic module coupled to the first clock and user signal value compression tunnel portal of the verification module, each partition logic module comprising: (d) a plurality of field programmable logic devices for emulating the user design wherein each field programmable logic device comprises, in addition to the user design, a circuit for a user signal compression tunnel, the circuit for a user signal compression tunnel coupled to at least one second clock and user signal compression tunnel portal, whereby a portion of the user design assigned to the programmable logic device communicates with portions of the user design assigned to other programmable logic devices; and

(iii) off chip storage wherein the embedded logic analyzer is coupled to: a circuit to receive a user signal compression address and to read signal values from off-chip storage and to transfer signal values to a user workstation; and

wherein the circuit for a user signal compression tunnel transfers an address when a signal value has been previously stored in off-chip storage.

2. A system as in claim 1 , wherein each circuit for a user signal compression tunnel compares signal values to signal values stored in off-chip storage; and stores new signal values into off-chip storage.

3. A system as in claim 2 , wherein each circuit for a user signal compression tunnel transfers to the user signal compression tunnel portal only addresses of off-chip stored values when signal values match stored signal values.

4. A system as in claim 1 , wherein each circuit for a user signal compression tunnel transfers to the user signal compression tunnel portal both a new signal value and an address in off-chip storage at which the new signal value shall be stored.

5. A system as in claim 1 , wherein the verification module further comprises: off-chip storage for user signal value compression, said storage communicatively coupled to a field programmable logic device containing an embedded logic analyzer.

6. An apparatus which comprises a printed circuit board communicatively coupled to:

(a) an interface to a user workstation;

(b) at least one field programmable logic device configured as a conventional embedded logic analyzer IP circuit description; and at least one first clock and user signal compression tunnel portal;

(c) at least one other field programmable logic devices for emulating the user design wherein each field programmable logic device comprises, a circuit for a user signal compression tunnel; the circuit for a user signal compression tunnel coupled to at least one second clock and user signal compression tunnel portal, whereby a portion of the user design assigned to the programmable logic device communicates with portions of the user design assigned to other programmable logic devices;

wherein the embedded logic analyzer is coupled to: a circuit to receive a user signal compression address and to read signal values from off-chip storage and to transfer signal values to a user workstation; and

wherein the circuit for a user signal compression tunnel transfers an address when a signal value has been previously stored in off-chip storage.

7. A computer-implemented method for functionally evaluating a user design by executing instructions on a processor coupled to non-transitory storage, to control a verification module and system controller comprising: an interface to a user workstation; at least one field programmable logic device configured as an conventional embedded logic analyzer IP circuit description; and at least one first clock and user signal compression tunnel portal; at least one System on Chip (SoC) partition logic module coupled to the first clock and user signal value compression tunnel portal of the verification module, each SoC partition logic module comprising: a plurality of field programmable logic devices (fpld) for emulating the user design; each fpld comprising a circuit for a user signal compression tunnel coupled to at least one second clock and user signal compression tunnel portal; the computer-implemented method comprising:

generating a top-level module including the user design and one or more embedded logic analyzer IP circuit descriptions by using a computer;

partitioning the user design into partitions, each partition suitable for configuration into one of the fplds by using said computer;

assigning to each fpld, by using a computer, a circuit for a user signal value compression tunnel through which the partition to be configured in that programmable logic device is allowed communication with other partitions configured in other programmable logic devices by using said computer; and

inserting an off-chip storage input/output management image for signal value compression into the image file which contains the embedded logic analyzer IP file on the verification module by using said computer.

8. A method as in claim 7 , further comprising: setting up a multi-chip access method for debugging a prototype across chip boundaries by using a computer.

9. A method as in claim 8 wherein setting up a multi-chip access method comprises: creating a file of signals desired for observability.

10. A method as in claim 9 further comprising: partitioning the top level module so that one or more embedded logic analyzer IP circuit descriptions are partitioned to the verification module whereby the interface to the user workstation provides one or more triggers and transmits signal values captured upon observation of each trigger by using said computer.

11. A method as in claim 10 further comprising: placing and routing each partition to an image file with spare resources suitable for configuring one of the programmable logic devices by using a computer.

12. A method as in claim 11 further comprising: a) selecting signals for analysis and b) determining optimum tunnel compression technology by using said computer.

13. A computer-implemented method for functionally evaluating a user design by executing instructions on a processor coupled to non-transitory storage, to control a verification module and system controller which includes an interface to a user workstation; at least one field programmable logic device configured as an conventional embedded logic analyzer IP circuit description; and at least one first clock and user signal compression tunnel portal; at least one System on Chip (SoC) partition logic module coupled to the first clock and user signal value compression tunnel portal of the verification module, each SoC partition logic module comprising: a plurality of field programmable logic devices (fpld) for emulating the user design; each fpld comprising a circuit for a user signal compression tunnel coupled to at least one second clock and user signal compression tunnel portal; the computer-implemented method comprising:

generating a top-level module including the user design and one or more embedded logic analyzer IP circuit descriptions by using a computer;

partitioning the user design into partitions, each partition suitable for configuration into one of the fplds by using said computer; and

assigning to each fpld, by using a computer, a circuit for a user signal value compression tunnel through which the partition to be configured in that programmable logic device is allowed communication with other partitions configured in other programmable logic devices by using said computer;

setting up a multi-chip access method for debugging a prototype across chip boundaries by creating a file of signals desired for observability;

partitioning the top level module so that one or more embedded logic analyzer IP circuit descriptions are partitioned to the verification module whereby the interface to the user workstation provides one or more triggers and transmits signal values captured upon observation of each trigger by using said computer;

placing and routing each partition to an image file with spare resources suitable for configuring one of the programmable logic devices by using a computer;

selecting signals for analysis;

determining optimum tunnel compression technology by using said computer;

inserting an off-chip storage input/output management image for signal value compression into the image file which contains the embedded logic analyzer IP file on the verification module by using said computer;

implementing the placed and routed image files in the programmable logic devices;

writing signal values to off-chip storage,

comparing new signal values to stored signal values,

transferring addresses of off-chip stored values when they match,

transferring an address and signal values when not matched to previously stored signal values, and

reading signal values from off-chip storage.