Ultra-high voltage N-type-metal-oxide-semiconductor (UHV NMOS) device and methods of manufacturing the same
An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer.
1. An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device, comprising
a substrate of P-type material;
a first high-voltage N-well (HVNW) region disposed in a portion of the substrate;
a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk;
a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate;
a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and
an n-type implant layer formed on the P-Top layer.
2. The device according to claim 1 , further comprising a field oxide (FOX) disposed at the first HVNW region and on the n-type implant layer, wherein the gate extended from the source and bulk PW to a portion of the FOX.
3. The device according to claim 1 , further comprising a PW space is disposed between the first HVNW region and a second HVNW region, wherein the second HVNW region is disposed in a high-side operation region of the substrate.
4. The device according to claim 3 , wherein at least two PWs separately formed in the PW space.
5. The device according to claim 3 , further comprising:
an inter-layer dielectric (ILD) layer disposed on the substrate; and
a first patterned metal layer disposed on the ILD layer.
6. The device according to claim 5 , wherein a portion of the first patterned metal layer overpass the PW space for high-voltage interconnection.
7. The device according to claim 5 , further comprising:
an inter-metal dielectric (IMD) layer disposed on the first patterned metal layer; and
a second patterned metal layer disposed on the IMD layer,
wherein at least one portion of the first and second patterned metal layers overpass the PW space for high-voltage interconnection.
8. The device according to claim 3 , further comprising:
a first N-doped buried layer (NBL) disposed adjacent to the first HVNW region and under the source and bulk PW.
9. The device according to claim 8 , further comprising:
a second N-doped buried layer (NBL) disposed adjacent to the second HVNW region in the high-side operation region.
10. The device according to claim 9 , further comprising:
a third N-doped buried layer (NBL) disposed between the drain and the PW space.
11. The device according to claim 1 , wherein the first HVNW region extends to the source and bulk PW.
12. The device according to claim 1 , wherein the n-type implant layer and P-Top layer beneath have substantially the same dimension.
13. The device according to claim 1 , wherein the n-type implant layer and P-Top layer beneath are plural split blocks within the first HVNW region, and between the drain and the source and bulk PW.