IP Library Granted Patent US 8,611,418
Granted Patent B2
US 8,611,418 · App. 11/644,354 · Granted Dec 17, 2013

Decoding a progressive JPEG bitstream as a sequentially-predicted hybrid video bitstream

Inventors: Kourosh Soroushian (San Jose, CA); K. Metin Uz (Eden Prairie, MN); Satish Vithal Joshi (Cupertino, CA)
Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,611,418
App. No.
11/644,354
Granted
Dec 17, 2013
Kind
B2
Abstract

An apparatus generally including a first circuit and a second circuit is disclosed. The first circuit may be configured to generate an intermediate bitstream by parsing a Joint Picture Expert Group (JPEG) bitstream carrying a picture. The intermediate bitstream generally includes one or more encoded frames each representing a portion of the picture. The second circuit may be configured to (i) generate one or more intermediate images by decoding the encoded frames and (ii) recreate the picture using the intermediate images.

Claims (64)

1. An apparatus comprising:

a first circuit configured to generate an intermediate bitstream by transcoding an input bitstream carrying a picture, wherein

(i) said input bitstream comprises a Joint Picture Expert Group (JPEG) bitstream,

(ii) said picture is represented by a plurality of discrete cosine transform coefficients in said input bitstream,

(iii) said discrete cosine transform coefficients form at least five bit-planes,

(iv) said intermediate bitstream comprises a Motion Picture Expert Group (MPEG) bitstream,

(v) said intermediate bitstream includes at least five encoded frames arranged in a sequence of one intra-frame followed by at least four consecutive predicted-frames and

(vi) each of said encoded frames represents a different subset of said bit-planes; and

a second circuit configured to

(i) generate a plurality of decoded images by decoding said encoded frames of said intermediate bitstream in said sequence and

(ii) recreate said picture by adding said decoded images to each other to rejoin said subsets of said bit-planes,

wherein each of said decoded images when added increases a respective resolution of each one of a plurality of pixel values in said picture.

2. The apparatus according to claim 1 , wherein said input bitstream comprises a progressive mode JPEG bitstream that gradually refines said picture in many passes.

3. The apparatus according to claim 1 , wherein said first circuit comprises a JPEG-to-MPEG transcoder.

4. The apparatus according to claim 1 , wherein

(i) a first of said encoded frames comprises an MPEG intra-frame carrying a plurality of most significant bits of index of coefficients of said discrete cosine transform coefficients and

(ii) said second circuit comprises an MPEG decoder modified to rejoin said subsets of said bit-planes.

5. The apparatus according to claim 4 , wherein

(i) a second of said encoded frames comprise an MPEG predicted-frame and

(ii) each of a plurality of macroblocks in said MPEG predicted-frame has a null motion vector that points to said MPEG intra-frame.

6. The apparatus according to claim 1 , wherein said second circuit is further configured to generate a plurality of scaled images by spatially scaling down said decoded images.

7. The apparatus according to claim 6 , wherein

(i) said second circuit further comprises a memory configured to buffer a first of said scaled images and

(ii) a first size of said memory is less than a second size of said picture.

8. The apparatus according to claim 7 , wherein said second circuit is further configured to

(i) generate an updated image by adding said first scaled image to a second of said scaled images and

(ii) store said updated image in said memory.

9. The apparatus according to claim 7 , wherein said second circuit is further configured to generate said scaled images by spatially decimating a plurality of rows in said decoded images, one of said rows at a time.

10. The apparatus according to claim 9 , wherein said second circuit is further configured to generate an updated image by adding said first scaled image to a second of said scaled images, one of said rows at a time.

11. The apparatus according to claim 1 , further comprising a third circuit configured to display said picture.

12. The apparatus according to claim 11 , wherein said second circuit is further configured to withhold said decoded images from said third circuit while adding said decoded images.

13. A method for decoding a picture, comprising the steps of:

(A) generating an intermediate bitstream by transcoding an input bitstream carrying said picture, wherein

(i) said input bitstream comprises a Joint Picture Expert Group (JPEG) bitstream

(ii) said picture is represented by a plurality of discrete cosine transform coefficients in said input bitstream,

(iii) said discrete cosine transform coefficients form at least five bit-planes,

(iv) said intermediate bitstream comprises a Motion Picture Expert Group (MPEG) bitstream,

(v) said intermediate bitstream includes at least five encoded frames arranged in a sequence of one intra-frame followed by at least four consecutive predicted-frames and

(vi) each of said encoded frames represents a different subset of said bit-planes;

(B) generating a plurality of decoded images by decoding said encoded frames of said intermediate bitstream in said sequence; and

(C) recreating said picture by adding said decoded images to each other to rejoin said subsets of said bit-planes,

wherein each of said decoded images when added increases a respective resolution of each one of a plurality of pixel values in said picture.

14. The method according to claim 13 , wherein said input bitstream comprises a progressive JPEG bitstream that gradually refines said picture in many passes.

15. The method according to claim 13 , wherein said encoded frames are generated by a JPEG-to-MPEG transcoding.

16. The method according to claim 13 , wherein

(i) an initial of said encoded frames comprises an MPEG intra-frame carrying a plurality of most significant bits of index coefficients of said discrete cosine transform coefficients and

(ii) said picture is recreated by an MPEG decoding modified to rejoin said subsets of said bit-planes.

17. The method according to claim 16 , wherein

(i) a next of said encoded frames comprises an MPEG predicted-frame and

(ii) each of a plurality of macroblocks in said MPEG predicted-frame has a null motion vector that points to said MPEG intra-frame.

18. The method according to claim 13 , further comprising the step of:

generating a plurality of scaled images by spatially scaling down said decoded images.

19. The method according to claim 18 , further comprising the step of:

buffering an initial of said scaled images in a memory,

wherein a first size of said memory is less than a second size of said picture.

20. The method according to claim 19 , further comprising the steps of:

generating an updated image by adding said initial scaled image to a next of said scaled images; and

storing said updated image in said memory.

21. The method according to claim 19 , further comprising the step of:

generating said scaled images by spatially decimating a plurality of rows in said decoded images, one of said rows at a time.

22. The method according to claim 13 , further comprising the step of:

transcoding a next picture into said intermediate bitstream substantially simultaneously with generating said decoded images.

23. The method according to claim 22 , further comprising the step of:

generating a plurality of next decoded images substantially simultaneously with recreating said picture.

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
MERGER Recorded Nov 14, 2013
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 031600/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2007
From: SOROUSHIAN, KOUROSH; UZ, K. METIN; JOSHI, SATISH VITHAL
To: LSI LOGIC CORPORATION
Reel/Frame 018936/0143 →
Continuity (2)
Provisional Application 60861786 · Nov 30, 2006
Related Publication 20080130746A1 · Jun 5, 2008