Granted Patent B2

US 8,614,902 · App. 12/981,128 · Granted Dec 24, 2013

Inventors: Frans Pansier (Nuenen, NL); Thomas Antonius Duerbaum (Baiersdorf, DE); Markus Schmid (Jettingen-Scheppach, DE); Klaus Mühlbauer (Friedenfels, DE); Johann Baptist Daniel Kuebrich (Schlüsselfeld, DE)

Assignee: NXP B.V.

Abstract

Claims (33)

1. A power factor correction stage comprising:

an input terminal configured to receive an input signal;

an output terminal configured to provide an output signal;

a first converter stage and at least one further converter stage, wherein each converter stage is connected to the input terminal and the output terminal, and each converter stage comprises a switch; and

a controller configured to operate the switch of the at least one converter stage;

wherein the controller is configured to operate the switch of the at least one further converter stage at a period of time after operation of the switch of the first converter stage for a current switching cycle, wherein the period of time is not equal to a period of an earlier switching cycle divided by the number of converter stages.

2. The power factor correction stage of claim 1 , wherein the controller is configured to operate the switch of the at least one converter stage at a period of time after operation of the switch of the first converter stage for a current switching cycle based on one of:

a fixed internal setting of the period of time value in the controller;

a modification of a fixed internal setting of the period of time value in the controller in accordance with user input; and

a value in a look-up table in accordance with at least one parameter value.

3. The power factor correction stage of claim 1 , wherein the controller is configured to operate the first converter stage in a variable switching frequency mode of operation.

4. The power factor correction stage of claim 3 , wherein the controller is configured to operate the first converter stage in a boundary conduction mode of operation.

5. The power factor correction stage of claim 1 , wherein the converter stages are boost converters.

6. The power factor correction stage of claim 1 , wherein the first converter stage and at least one of the further converter stages are interleaved converter stages.

7. The power factor correction stage of claim 1 , wherein the controller is configured to deactivate at least one of the converter stages if the required output level falls below a threshold value.

8. An integrated circuit comprising the control functionality of the power factor correction stage of claim 1 .

9. A method of operating an interleaved power factor correction stage, the method comprising:

operating a switch of a first converter stage; and

operating a switch of at least one further converter stage at a period of time after operation of the switch of the first converter stage, wherein the period of time is not equal to a period of an earlier switching cycle divided by the number of converter stages.

10. The method of claim 9 , wherein operating the switch of the first converter stage comprises:

operating the switch of the first converter stage such that the combined output of the first converter stage and the at least one converter stage provides a required output level.

11. A method of designing an interleaved power factor correction circuit, comprising:

applying at least one test signal to the power factor correction circuit with different time periods between switching operations of the interleaved converter stages, wherein the different time periods correspond to different proportions of an earlier switching cycle;

performing a spectral analysis of the performance of the power factor correction circuit; and

identifying a period of time that provides an acceptable level of disturbance in the spectral analysis;

wherein the identified period of time is not equal to a period of the earlier switching cycle divided by the number of converter stages.

12. The method of claim 11 , wherein the method is performed by computer simulation.

13. The method of claim 11 , further comprising:

applying the identified period of time to a controller of a power factor correction circuit.

14. The method of claim 11 , wherein identifying a period of time that provides an acceptable level of disturbance in the spectral analysis comprises performing a determination of the minimum requirements of an associated EMI filter.

15. A method of operating an interleaved power factor correction circuit comprising:

performing the method of designing a power correction circuit of claim 11 ; and

operating the switches of the interleaved power factor correction circuit in accordance with the identified period of time.

Assignments (10)

Priority Claims (1)

Continuity (1)