Semiconductor device and driving method thereof
View Patent ↗A semiconductor device including a memory cell formed using a wide bandgap semiconductor, for example, an oxide semiconductor is provided. The semiconductor device includes a potential change circuit having a function of outputting a potential lower than a reference potential for reading data from the memory cell. With the use of the wide bandgap semiconductor, an off-state current of a transistor included in the memory cell can be sufficiently reduced, and the semiconductor device which can hold data for a long period can be provided.
1. A semiconductor device comprising:
a wiring;
a memory cell comprising:
a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; and
a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region; and
a reading circuit comprising a load, a clocked inverter, and a third transistor,
wherein a material of the first channel formation region is different from that of the second channel formation region,
wherein the third transistor comprises a third gate electrode, a third source electrode, a third drain electrode, and a third channel formation region,
wherein an input terminal of the clocked inverter is electrically connected to the load and one of the first source electrode and the first drain electrode through the wiring,
wherein an output terminal of the clocked inverter is electrically connected to one of the third source electrode and the third drain electrode, and
wherein the other of the third source electrode and the third drain electrode is electrically connected to a power supply potential.
2. The semiconductor device according to claim 1 ,
wherein the first transistor is a p-channel transistor, and
wherein the second transistor is an n-channel transistor.
3. The semiconductor device according to claim 1 ,
wherein the second channel formation region includes an oxide semiconductor.
4. The semiconductor device according to claim 1 , further comprising a latch circuit electrically connected to the output terminal of the clocked inverter.
5. The semiconductor device according to claim 1 ,
wherein the wiring is electrically connected to one of the second source electrode and the second drain electrode.
6. A semiconductor device comprising:
a first wiring;
a second wiring;
a memory cell comprising:
a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region;
a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region; and
a capacitor, wherein a first electrode of the capacitor is electrically connected to the first gate electrode and one of the second source electrode and the second drain electrode and wherein a second electrode of the capacitor is electrically connected to the second wiring; and
a reading circuit comprising a load, a clocked inverter, and a third transistor,
wherein a material of the first channel formation region is different from that of the second channel formation region,
wherein the third transistor comprises a third gate electrode, a third source electrode, a third drain electrode, and a third channel formation region,
wherein an input terminal of the clocked inverter is electrically connected to the load and one of the first source electrode and the first drain electrode through the first wiring,
wherein an output terminal of the clocked inverter is connected to one of the third source electrode and the third drain electrode,
wherein the other of the third source electrode and the third drain electrode is electrically connected to a power supply potential,
wherein the third transistor is configured to be turned OFF whenever a potential of the second wiring is changed, and
wherein a clock signal having a high-level potential is input to a clock signal line in the clocked inverter whenever the potential of the second wiring is changed.
7. The semiconductor device according to claim 6 ,
wherein the first transistor is a p-channel transistor, and
wherein the second transistor is an n-channel transistor.
8. The semiconductor device according to claim 6 ,
wherein the second channel formation region includes an oxide semiconductor.
9. The semiconductor device according to claim 6 , further comprising a latch circuit electrically connected to the output terminal of the clocked inverter.
10. The semiconductor device according to claim 6 ,
wherein the first wiring is electrically connected to one of the second source electrode and the second drain electrode.
11. A driving method of a semiconductor device comprising:
a first wiring;
a second wiring;
a memory cell comprising:
a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region;
a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region; and
a capacitor, wherein a first electrode of the capacitor is electrically connected to the first gate electrode and one of the second source electrode and the second drain electrode and wherein a second electrode of the capacitor is electrically connected to the second wiring; and
a reading circuit comprising a load, a clocked inverter, and a third transistor,
wherein a material of the first channel formation region is different from that of the second channel formation region,
wherein the third transistor comprises a third gate electrode, a third source electrode, a third drain electrode, and a third channel formation region,
wherein an input terminal of the clocked inverter is electrically connected to the load and one of the first source electrode and the first drain electrode through the first wiring,
wherein an output terminal of the clocked inverter is connected to one of the third source electrode and the third drain electrode, and
wherein the other of the third source electrode and the third drain electrode is electrically connected to a power supply potential, the driving method comprising the steps of:
gradually changing a first potential input to the second wiring from a second potential to a third potential;
gradually changing a fourth potential input to the first wiring in accordance with the change of the first potential, the fourth potential being determined by a resistance division of the load and the first transistor;
inputting a clock signal and an inversed clock signal to the clocked inverter whenever the first potential is changed;
outputting an output signal from the clocked inverter whenever the clock signal and the inversed clock signal are input to the clocked inverter; and
inputting the clock signal or the inversed clock signal to the third gate electrode and turning off the third transistor while the clock signal or the inversed clock signal is input to the third gate electrode.
12. The driving method according to claim 11 ,
wherein the first transistor is a p-channel transistor, and
wherein the second transistor is an n-channel transistor.
13. The driving method according to claim 11 ,
wherein the second channel formation region includes an oxide semiconductor.
14. The driving method according to claim 11 ,
wherein the semiconductor device further comprises a latch circuit electrically connected to the output terminal of the clocked inverter.
15. The driving method according to claim 11 ,
wherein the first wiring is electrically connected to one of the second source electrode and the second drain electrode.
16. The driving method according to claim 11 ,
wherein the third transistor is a p-channel transistor,
wherein the power supply potential is VDD, and
wherein the inversed clock signal is input to the third gate electrode whenever the first potential is changed.
17. The driving method according to claim 11 ,
wherein the third transistor is an n-channel transistor,
wherein the power supply potential is GND, and
wherein the clock signal is input to the third gate electrode whenever the first potential is changed.