Nonvolatile memory system and related method of performing erase refresh operation

1. A flash memory system, comprising:

a flash memory comprising a plurality of memory blocks; and

a memory controller that performs multiple successive read retry operations on a memory block in which an uncorrectable read error has been detected in a read operation using a normal read voltage, until a correctable data value is read, and thereafter controls the flash memory to perform an erase refresh operation on the memory block;

wherein the memory controller performs the read retry operation using a varied read voltage that is produced by incrementing or decrementing the normal read voltage in each of the successive read retry operations according to whether the normal read voltage is designated for reading a first data state or a second data state.

2. The flash memory system of claim 1 , wherein the flash memory stores and updates read retry information associated with each of the successive read retry operations.

3. The flash memory system of claim 2 , wherein the read retry information comprises at least one of (a) a number read retry operations that have been performed on the memory block, (b) an address of the memory block, and (c) a value of the varied read voltage used to read correctable data in the read retry operations.

4. The flash memory system of claim 2 , wherein the memory controller controls the erase refresh operation based on the read retry information.

5. The flash memory system of claim 1 , wherein the read retry operations are performed repeatedly until a correctable data value is read.

6. The flash memory system of claim 1 , wherein the first data state is an erase state of memory cells in the flash memory device.

7. The flash memory system of claim 1 , wherein the second data state is a highest program state of memory cells in the flash memory device.

8. A method of operating a memory device comprising a plurality of memory blocks, the method comprising:

performing multiple successive read retry operations on a memory block in which an uncorrectable read error has been detected in a read operation using a normal read voltage, until a correctable data value is read from the memory block; and

performing an erase refresh operation on the memory block after at least one of the read retry operations has been performed, in response to read retry information associated with the at least one read retry operation

wherein the memory controller performs the read retry operations using a varied read voltage that is produced by incrementing or decrementing the normal read voltage in each of the successive read retry operations according to whether the normal read voltage is designated for reading a first data state or a second data state.

9. The method of claim 8 , wherein the read retry operations are performed repeatedly until a correctable data value is read.

10. The method of claim 8 , wherein the read retry information comprises at least one of (a) a number read retry operations that have been performed on the memory block, (b) an address of the memory block, and (c) a value of the varied read voltage which is used to read correctable data in the read retry operation.

11. The method of claim 8 , wherein the first data state is an erase state of memory cells in the memory device.

12. The method of claim 8 , wherein the second data state is a highest program state of memory cells in the memory device.

13. A method of operating a nonvolatile memory device comprising a plurality of memory blocks, the method comprising:

reading data from a selected memory block in a read operation using a normal read voltage;

detecting whether an uncorrectable error exists in the data;

upon detecting the uncorrectable error, performing a plurality of read retry operations on the selected memory block using a varied read voltage until a correctable error exists in the data that is read; and

moving the data that has been read to a free memory block and erasing the selected memory block;

wherein the varied read voltage is incremented or decremented in each successive read retry operation according to whether the normal read voltage is designated for reading a first data state or a second data state.

14. The method of claim 13 , further comprising:

marking the selected memory block as an invalid block or a bad block upon detecting that a number of erasing/programming cycles of the selected memory block is greater than or equal to a predetermined reference value.

15. The method of claim 13 , wherein reading the data from the selected memory block comprises:

determining whether a prior read retry operation has correctable read data from the selected memory block;

upon determining that a prior read retry operation has correctable read data from the selected memory block, applying a varied read voltage from the prior read retry operation to the selected memory block; and

upon determining that no prior read retry operation has correctable read data from the selected memory block, applying the normal read voltage to the selected memory block.

16. The method of claim 13 , wherein the first data state is an erase state of memory cells in the nonvolatile memory device.

17. The method of claim 13 , wherein the second data state is a highest program state of memory cells in the nonvolatile memory device.