Printed wiring board
A printed wiring board including a wiring substrate provided with at least one conductor circuit, a solder resist layer provided on the surface of the wiring substrate, at least one conductor pad formed from a part of the conductor circuit exposed from an opening provided in the solder resist layer, and at least one solder bump for mounting electronic parts on the conductor pad. In the printed wiring board, since the at least one conductor pad is aligned at a pitch of about 200 μm or less, and a ratio (W/D) of a diameter W of the solder bump to an opening diameter D of the opening formed in the solder resist layer is about 1.05 to about 1.7, connection reliability and insulation reliability can be easily improved.
1. A printed wiring board comprising:
a wiring substrate;
a build-up wiring layer formed by laminating conductor circuits and at least one interlaminar resin insulating layer alternately on the wiring substrate, the built up wiring layer having an outermost interlaminar resin insulating layer;
a plurality of filled vias each filled with a plated conductor within a respective opening provided in the outermost interlaminar resin insulating layer, wherein each filled via electrically connects first and second conductor circuits situated in mutually different layers;
a solder resist layer provided on the outermost interlaminar resin insulating layer and an outermost conductor circuit of said first and second conductor circuits;
a plurality of openings formed in the solder resist layer to expose a plurality of parts of a the outermost conductor circuit which forms a plurality of conductor pads for mounting electronic parts, respectively, wherein each of the plurality of conductor pads has a filled via surface having a depression or protrusion in the range of about −5 μm to about +5 μm in relation to a surface thickness of the outermost conductor circuit; and
a plurality of solder bumps formed on the plurality of conductor pads, respectively wherein the conductor pads are aligned at a pitch of about 200 μm or less, and a ratio W/D of a diameter W of the solder bumps to an opening diameter D of the openings formed in the solder resist layer is about 1.05 to about 1.26.
2. The printed wiring board of claim 1 , wherein the openings of the solder resist layer are formed in a tapered fashion such that an opening diameter D 1 at the top surface thereof is larger than an opening diameter D 2 at the bottom surface thereof.
3. The printed wiring board of claim 2 , wherein the difference between the opening diameters D 1 -D 2 is about 5 μm to about 20 μm.
4. The printed wiring board of claim 1 , wherein the surface of the solder resist layer is subjected to a flattening treatment in at least an electronic parts mounting region.
5. The printed wiring board of claim 4 , wherein the flattened surface of the solder resist layer is further subjected to a roughening treatment.
6. The printed wiring board of claim 4 , wherein the flattened surface of the solder resist layer is about 0.8 μm to about 3.0 μm in maximum surface roughness.
7. The printed wiring board of claim 6 , wherein roughness of the roughened surface of the solder resist layer is smaller than the maximum surface roughness of the flattened surface, and about 0.2 μm to about 0.5 μM at an arithmetic mean roughness.
8. The printed wiring board of claim 1 , wherein the solder bumps are in contact with wall surfaces of the openings in the solder resist layer, respectively.
9. The printed wiring board of claim 1 , wherein the solder bumps are formed by loading solder bumps on the conductor pads, respectively.
10. The printed wiring board of claim 1 , wherein the conductor pads are position to align with respective contacts of the electric parts to be mounted on the printed wiring board.
11. A printed wiring board comprising:
a wiring substrate;
a build-up wiring layer formed by laminating conductor circuits and at least one interlaminar resin insulating layer alternately on the wiring substrate, the built up wiring layer having an outermost interlaminar resin insulating layer;
a plurality of filled vias each filled with a plated conductor within a respective opening provided in the outermost interlaminar resin insulating layer, wherein each filled via electrically connects first and second conductor circuits situated in mutually different layers;
a solder resist layer provided on the outermost interlaminar resin insulating layer and an outermost conductor circuit of said first and second conductor circuits;
a plurality of openings formed in the solder resist layer to expose a plurality of parts of the outermost conductor circuit which forms a plurality of conductor pads for mounting electronic parts, respectively, wherein each of the plurality of conductor pads has a filled via surface having a depression or protrusion in the range of about −5 μm to about +5 μm in relation to a surface thickness of the outermost conductor circuit; and
a plurality of solder bumps formed on the plurality of conductor pads, respectively;
at least one electric part mounted on the conductor pads through the solder bumps; and
an under fill resin sealing between the electronic part and the solder resist layer, wherein the conductor pads are aligned at a pitch of about 200 μm or less, and a ratio W/D of a diameter W of the solder bumps to an opening diameter D of the openings formed in the solder resist layer is about 1.05 to about 1.26.
12. The printed wiring board of claim 11 , wherein the openings of the solder resist layer are formed in a tapered fashion such that an opening diameter D 1 at the top surface thereof is larger than an opening diameter D 2 at the bottom surface thereof.
13. The printed wiring board of claim 12 , wherein the difference between the opening diameters D 1 -D 2 is about 5 μm to about 20 μm.
14. The printed wiring board of claim 11 , wherein the surface of the solder resist layer is subjected to a flattening treatment in at least an electronic parts mounting region.
15. The printed wiring board of claim 14 , wherein the flattened surface of the solder resist layer is further subjected to a roughening treatment.
16. The printed wiring board of claim 14 , wherein the flattened surface of the solder resist layer is about 0.8 μm to about 3.0 μm in maximum surface roughness.
17. The printed wiring board of claim 11 , wherein the solder bumps are in contact with wall surfaces of the openings in the solder resist layer, respectively.
18. The printed wiring board of claim 11 , wherein the solder bumps are formed by loading solder bumps on the conductor pads, respectively.
19. The printed wiring board of claim 11 , wherein the conductor pads are position to align with respective contacts of the electric parts to be mounted on the printed wiring board.