IP Library Granted Patent US 8,624,261
Granted Patent B2
US 8,624,261 · App. 13/220,005 · Granted Jan 7, 2014

Nitride semiconductor device

Inventor: Kentaro Ikeda (Kanagawa-ken, JP)
Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,624,261
App. No.
13/220,005
Granted
Jan 7, 2014
Kind
B2
Abstract

According to one embodiment, a nitride semiconductor device includes a first, a second, a third and a fourth transistor of n-type channel and a resistor. The first transistor has a first gate, a first source, and a first drain. The second transistor has a second gate, a second source electrically connected to the first gate, and a second drain. The third transistor has a third gate, a third source electrically connected to the first source, and a third drain electrically connected to the first gate and the second source. The fourth transistor has a fourth gate electrically connected to the third gate, a fourth source electrically connected to the first source and the third source, and a fourth drain electrically connected to the second gate. The resistor has one end electrically connected to the second drain and one other end electrically connected to the second gate and the fourth drain.

Claims (55)

1. A nitride semiconductor device, comprising:

a first transistor of n-type channel having a first gate, a first source, and a first drain and including a nitride semiconductor;

a second transistor of n-type channel having a second gate, a second source electrically connected to the first gate, and a second drain, the second transistor including a nitride semiconductor;

a third transistor of n-type channel having a third gate, a third source electrically connected to the first source, and a third drain electrically connected to the first gate and the second source, the third transistor including a nitride semiconductor;

a fourth transistor of n-type channel having a fourth gate electrically connected to the third gate, a fourth source electrically connected to the first source and the third source, and a fourth drain electrically connected to the second gate, the fourth transistor including a nitride semiconductor;

a resistor having one end electrically connected to the second drain and one other end electrically connected to the second gate and the fourth drain;

a drain electrode pad electrically connected to the fourth drain;

a source electrode pad electrically connected to the first source, the third source and the fourth source;

a gate electrode pad electrically connected to the fourth gate and the third gate; and

a power-supply electrode pad electrically connected to the second drain and the one end of the resistor.

2. The device according to claim 1 , wherein

a ratio of an area of an active portion of the second transistor to an area of an active portion of the first transistor, a ratio of an area of an active portion of the third transistor to the area of the active portion of the first transistor, and a ratio of an area of an active portion of the fourth transistor to the area of the active portion of the first transistor are 5×10 −5 or more and 5×10 −1 or less.

3. The device according to claim 2 , wherein

the area of the active portion of the fourth transistor is not more than the area of the active portion of the second transistor and not more than the area of the active portion of the third transistor.

4. The device according to claim 1 , wherein

a ratio of an area of an active portion of the second transistor to an area of an active portion of the first transistor and a ratio of an area of an active portion of the fourth transistor to the area of the active portion of the first transistor are 5×10 −5 or more and 5×10 −1 or less.

5. The device according to claim 1 , wherein

a ratio of an area of an active portion of the third transistor to an area of an active portion of the first transistor is 5×10 −1 or less.

6. The device according to claim 1 , further comprising:

a nitride semiconductor layer,

each of channels included in each of the first, second, third, and fourth transistors being provided inside the nitride semiconductor layer.

7. The device according to claim 1 , further comprising:

a substrate having a heterojunction,

the first, second, third, and fourth transistors being provided on the substrate.

8. The device according to claim 1 , further comprising:

a nitride semiconductor layer including:

a first layer made of GaN; and

a second layer provided on the first layer and made of In x Al y Ga 1-x-y N (0≦x<1, 0<y<1),

the resistor including a part of the nitride semiconductor layer.

9. The device according to claim 8 , wherein

the resistor includes a recess provided in the second layer.

10. The device according to claim 1 , wherein

the resistor includes a two-dimensional electron gas.

11. The device according to claim 1 , further comprising:

a conductive portion electrically connected to the second gate, the fourth drain and the one other end of the resistor.

12. The device according to claim 1 , wherein

the power-supply electrode pad is applied with a voltage of an absolute value of 3 volts or more and 20 volts or less.

13. The device according to claim 1 , further comprising:

a capacitor having one end electrically connected to the second drain and the one end of the resistor and having one other end electrically connected to the first source, the third source, and the fourth source.

14. The device according to claim 13 , further comprising:

a nitride semiconductor layer including:

a first layer made of GaN; and

a second layer provided on the first layer and made of In x Al y Ga 1-x-y N (0≦x<1, 0<y<1),

the capacitor including a part of the nitride semiconductor layer.

15. The device according to claim 14 , wherein the capacitor includes:

an insulating film provided on the second layer; and

a capacitor electrode provided on the insulating film.

16. The device according to claim 15 , wherein

the insulating film includes at least one selected from the group consisting of SiO 2 , SiN, Al 2 O 3 , TiO 2 , BaTiO 3 , SrTiO 3 , (Ba,Sr)TiO 3 , Ta 2 O 5 , LiTaO 3 , HfO 2 and ZrO 2 .

17. The device according to claim 13 , wherein

the capacitor includes a two-dimensional electron gas.

18. The device according to claim 13 , wherein

the capacitor has a capacity not less than an input capacity at a threshold voltage of the first transistor.

19. The device according to claim 18 , wherein

the capacity of the capacitor is not more than 100 times the input capacity at the threshold voltage of the first transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2011
From: IKEDA, KENTARO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 027207/0366 →
Priority Claims (1)
JP 2011-53604 · Mar 10, 2011 · national
Continuity (1)
Related Publication 20120228625A1 · Sep 13, 2012