Semiconductor device and method of fabricating the same
The invention relates to a semiconductor device, wherein a storage node contact hole is made large to solve any problem caused during etching a storage node contact hole with a small CD, a landing plug is formed to lower plug resistance. A semiconductor device according to the invention comprises: first and second active regions formed in a substrate, the first and second active being adjacent to each other, each of the first and second active regions including a bit-line contact region and a storage node contact region and a device isolation structure; a word line provided within a trench formed in the substrate; first and second storage node contact plugs assigned to the first and second active regions, respectively, the first and second storage node contact plugs being separated from each other by a bit line groove; and a bit line formed within the bit-line groove.
1. A semiconductor device, comprising:
first and second active regions formed in a substrate, the first and second active regions being adjacent to each other and separated by a device isolation structure, each of the first and second active regions including a bit-line contact region and a storage node contact region;
a word line provided within a trench formed in the substrate;
first and second storage node contact plugs assigned to the first and second active regions, respectively, the first and second storage node contact plugs being separated from each other by a bit line groove; and
a bit line formed within the bit-line groove; and
landing plugs formed over the bit-line contact and storage node contact regions,
wherein the bit-line contact region is a region between neighboring word lines, and the storage node contact region is a region between the word line and the device isolation structure.
2. The semiconductor device of claim 1 , wherein the landing plugs are formed through a selective epitaxial growth process.
3. The semiconductor device of claim 1 , further comprising:
an interlayer dielectric formed over the word lines and the device isolation structure.
4. The semiconductor device of claim 1 , wherein the word line comprises:
a gate conductive layer provided within the trench of the substrate; and
a capping layer formed over the gate conductive layer within the trench.
5. The semiconductor device of claim 1 , further comprising:
a nitride spacer formed on side walls of the bit-line groove.
6. The semiconductor device of claim 1 , wherein the bit line comprises:
a barrier metal layer contacting side walls and a bottom surface of the bit-line groove; and
a bit-line conductive layer contacting the barrier metal layer.
7. The semiconductor device of claim 6 , further comprising:
a silicide layer provided between the barrier metal layer and the bit-line conductive layer.
8. The semiconductor device of claim 1 , wherein the surface of the landing plugs have substantially the same height as a surface of the device isolation structure.
9. A semiconductor device, comprising:
first and second active regions formed in a substrate, the first and second active regions being adjacent to each other and separated by a device isolation structure, each of the first and second active regions including a bit-line contact region and a storage node contact region;
first and second storage node contact plugs assigned to the first and second active regions, respectively, the first and second storage node contact plugs being separated from each other by a bit line groove; and
landing plugs formed over the bit-line contact and storage node contact regions,
wherein the bit-line contact region is a region between neighboring word lines, and the storage node contact region is a region between the word line and the device isolation structure.
10. The semiconductor device of clam 9 , further comprising:
a word line provided within a trench formed in the substrate.
11. The semiconductor device of claim 10 , further comprising:
an interlayer dielectric formed over the word lines and the device isolation structure.
12. The semiconductor device of claim 10 , wherein the word line comprises:
a gate conductive layer provided within the trench of the substrate; and
a capping layer formed over the gate conductive layer within the trench.
13. The semiconductor device of clam 9 , further comprising:
a bit line formed within the bit-line groove.
14. The semiconductor device of claim 13 , wherein the bit line comprises:
a barrier metal layer contacting side walls and a bottom surface of the bit-line groove; and
a bit-line conductive layer contacting the barrier metal layer.
15. The semiconductor device of claim 14 , further comprising:
a silicide layer provided between the barrier metal layer and the bit-line conductive layer.
16. The semiconductor device of claim 9 , wherein the landing plugs are formed through a selective epitaxial growth process.
17. The semiconductor device of claim 9 , further comprising:
a nitride spacer formed on side walls of the bit-line groove.
18. The semiconductor device of claim 9 , wherein the surface of the landing plugs have substantially the same height as a surface of the device isolation structure.