Using a DMA engine to automatically validate DMA data paths
The disclosed embodiments provide a system that uses a DMA engine to automatically validate DMA data paths for a computing device. During operation, the system configures the DMA engine to perform a programmable DMA operation that generates a sequence of memory accesses which validate the memory subsystem and DMA paths of the computing device. For instance, the operation may include a sequence of reads and/or writes that generate sufficient data traffic to exercise the computing device's I/O controller interface and DMA data paths to memory to a specified level. The system initiates this programmable DMA operation, and then checks outputs for the operation to confirm that the operation executed successfully.
1. A computer-implemented method for using a DMA engine to automatically validate DMA data paths for a computing device, the method comprising:
configuring the DMA engine to perform a programmable DMA operation that generates a sequence of memory accesses which validate the memory subsystem and DMA paths of the computing device;
initiating the programmable DMA operation; and
checking an output for the programmable DMA operation to confirm that the programmable DMA operation executed successfully,
wherein configuring and initiating the programmable DMA operation comprises configuring a set of registers for the DMA engine to specify an I/O test pattern.
2. The computer-implemented method of claim 1 , wherein the programmable DMA operation initiates a programmable sequence of accesses that generates sufficient data traffic to exercise the computing device's I/O interface and DMA data paths to memory to a desired level.
3. The computer-implemented method of claim 2 , wherein generating the sufficient data traffic comprises generating data access patterns that exercise the I/O bandwidth of the computing device to the desired level and confirm memory system coherency for the computing device.
4. The computer-implemented method of claim 3 , wherein exercising the I/O bandwidth of the computing device to the desired level facilitates:
detecting a mismatch between functional and performance capabilities of the computing device's I/O subsystem and the functional and performance capabilities of other I/O devices configured to communicate with the computing device; and
exposing latent bugs or throughput bottlenecks in the computing device's I/O subsystem.
5. The computer-implemented method of claim 4 , wherein traffic generated by the DMA engine is multiplexed with I/O traffic from one or more external I/O devices.
6. The computer-implemented method of claim 2 ,
wherein the computing device is a processor; and
wherein the programmable DMA operation is initiated in a chip testing environment.
7. The computer-implemented method of claim 1 , wherein the I/O test pattern comprises at least one of the following:
a revolving pattern of read operations that load a known pattern of distinctive data values from the memory subsystem into a set of data registers in the DMA engine; and
a revolving pattern of write operations that generate a known pattern of distinctive data values in the DMA engine and transfer them to cachelines in the memory subsystem.
8. The computer-implemented method of claim 7 , wherein the revolving pattern includes unaligned accesses that trigger read-modify-write sub-operations, thereby stressing the memory and cache coherency subsystem.
9. The computer-implemented method of claim 7 , wherein the computing device does not include a memory device, wherein initiating the programmable DMA operation comprises:
sending a pseudo-random stream of data generated in a memory controller to the DMA engine;
XORing the pseudo-random stream of data into one or more data registers in the DMA engine; and
comparing the resulting checksum in the one or more data registers with a known checksum value for the pseudo-random stream of data.
10. The computer-implemented method of claim 1 , wherein configuring the set of registers comprises configuring a set of control and status registers for the DMA engine.
11. The computer-implemented method of claim 10 , wherein configuring and initiating the programmable DMA operation further comprises configuring the set of control and status registers to specify a duration.
12. A computing device configured to use a DMA engine to automatically validate DMA data paths, comprising:
a processor;
a memory subsystem; and
a DMA engine configured to generate a programmable sequence of memory accesses for a programmable DMA operation;
wherein the DMA engine is further configured to receive an initiating signal that initiates the programmable DMA operation;
wherein, upon completing the programmable DMA operation, the DMA engine is further configured to check an output of the programmable DMA operation to confirm that the programmable DMA operation executed successfully;
wherein configuring and initiating the programmable DMA operation comprises configuring a set of registers for the DMA engine to specify an I/O test pattern; and
wherein successfully executing the programmable DMA operation automatically validates the memory subsystem and DMA paths of the computing device.
13. The computing device of claim 12 , wherein the programmable DMA operation initiates a programmable sequence of accesses that generates sufficient data traffic to exercise the computing device's I/O interface and DMA data paths to memory to a desired level.
14. The computing device of claim 13 , wherein generating the sufficient data traffic intensity comprises generating data access patterns that exercise the I/O bandwidth of the computing device to the desired level and confirm memory system coherency for the computing device.
15. The computing device of claim 14 , wherein exercising the I/O bandwidth of the computing device to the desired level facilitates:
detecting a mismatch between functional and performance capabilities of the computing device's I/O subsystem and the functional and performance capabilities of external I/O devices configured to communicate with the computing device; and
exposing latent bugs or throughput bottlenecks in the computing device's I/O subsystem.
16. The computing device of claim 15 , wherein traffic generated by the DMA engine is multiplexed with I/O traffic from one or more external I/O devices.
17. The computing device of claim 13 ,
wherein the DMA engine is incorporated into the processor; and
wherein the programmable DMA operation is initiated in a chip testing environment.
18. The computing device of claim 12 , wherein the I/O test pattern comprises at least one of the following:
a revolving pattern of read operations that load a known pattern of distinctive data values from the memory subsystem into a set of data registers in the DMA engine; and
a revolving pattern of write operations that generate a known pattern of distinctive data values in the DMA engine and transfer them to cachelines in the memory subsystem.
19. The computing device of claim 18 , wherein the revolving pattern includes unaligned accesses that trigger read-modify-write sub-operations, thereby stressing the memory and cache coherency subsystem.
20. A non-transitory computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for using a DMA engine to automatically validate DMA data paths for a computing device, the method comprising:
configuring the DMA engine to perform a programmable DMA operation that generates a sequence of memory accesses which validate the memory subsystem and DMA paths of the computing device;
initiating the programmable DMA operation; and
checking an output for the programmable DMA operation to confirm that the programmable DMA operation executed successfully,
wherein configuring and initiating the programmable DMA operation comprises configuring a set of registers for the DMA engine to specify an I/O test pattern.